TS-7250-V3 ADC Header: Difference between revisions

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The ADC header supports 5 channels of 0-30VDC ADC.  Of these 5, 3 channels support sampling 0-20mA current loops.  These channels are sampled from /sys/devices/platform/soc/2100000.aips-bus/2198000.adc/iio:device0#/.
The ADC header supports 5 channels of 0-30VDC ADC.  Of these 5, 3 channels support sampling 0-20mA current loops.  These channels are sampled from:
 
For example:
<source lang=bash>
<source lang=bash>
# Disable current loops:
iio_attr -c 2198000.adc voltage0
 
iio_attr -c 2198000.adc voltage1
 
iio_attr -c 2198000.adc voltage5
iio_attr -c 2198000.adc voltage8
iio_attr -c 2198000.adc voltage9
</source>
</source>
See the [[#ADC|ADC section]] for more details on sampling these pins.


{|  
{|  
Line 20: Line 21:
|-
|-
| 1
| 1
| GPIO1_IO00/ADC?
| 2198000.adc/voltage0
|-
|-
| 2
| 2
Line 26: Line 27:
|-
|-
| 3
| 3
| GPIO1_IO01/ADC?
| 2198000.adc/voltage1
|-
|-
| 4
| 4
Line 32: Line 33:
|-
|-
| 5
| 5
| GPIO1_IO05/ADC?
| 2198000.adc/voltage5
|-
|-
| 6
| 6
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|-
|-
| 7
| 7
| GPIO1_IO08/ADC?
| 2198000.adc/voltage8
|-
|-
| 8
| 8
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|-
|-
| 9
| 9
| GPIO1_IO09/ADC?
| 2198000.adc/voltage9 [[#TS-7250-V3 Supervisory Low Power Mode|WAKE_UP#]]
|-
|-
| 10
| 10
Line 52: Line 53:
|  
|  


[[File:TS-7250-V3-ADC.png|300px]]
[[File:TS-7250-V3-ADC.svg|300px]]


|}
|}

Latest revision as of 15:09, 6 April 2023

The ADC header supports 5 channels of 0-30VDC ADC. Of these 5, 3 channels support sampling 0-20mA current loops. These channels are sampled from: 

iio_attr -c 2198000.adc voltage0
iio_attr -c 2198000.adc voltage1
iio_attr -c 2198000.adc voltage5
iio_attr -c 2198000.adc voltage8
iio_attr -c 2198000.adc voltage9

See the ADC section for more details on sampling these pins.

Signals Pin Layout
Pin Signal
1 2198000.adc/voltage0
2 GND
3 2198000.adc/voltage1
4 GND
5 2198000.adc/voltage5
6 GND
7 2198000.adc/voltage8
8 GND
9 2198000.adc/voltage9 WAKE_UP#
10 GND

TS-7250-V3-ADC.svg

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