TS-7250-V3 DIO Header: Difference between revisions

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The DIO header is a 0.1" pitch 2x8 header including SPI and GPIO. All pins on this header are 5V tolerant except SPI output pins.  All of these DIO includes pullups.
The DIO header is a 0.1" pitch 2x8 header including SPI and GPIO. All pins on this header are 5V tolerant except SPI output pins.  All of these DIO includes pullups.


{|  
{|  
Line 9: Line 9:
|-
|-
! Pin
! Pin
! IO Type
! Signal
! Signal
|-
|-
| 1
| 1
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 1]]
| [[#GPIO|GPIO Bank 5 IO 1]]
|-
|-
| 2
| 2
|
| GND
| GND
|-
|-
| 3
| 3
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 2]]
| [[#GPIO|GPIO Bank 5 IO 2]]
|-
|-
| 4
| 4
| [[#GPIO|Current Sink Output Bank 0 IO 30]] <ref>When this pin is a high output it enables a FET to ground.</ref>
| Open drain. High drives ground, low is tristate.
| [[#GPIO|Current Sink Output Bank 0 IO 30]]  
|-
|-
| 5
| 5
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 3]] / [[#UARTs|ttyS14 TX]]
| [[#GPIO|GPIO Bank 5 IO 3]] / [[#UARTs|ttyS14 TX]]
|-
|-
| 6
| 6
| [[#IO specifications|FPGA 3.3-V LVTTL]]
| [[#SPI|spidev 4.0 Chip Select]] / [[#GPIO|GPIO Bank 5 IO 11]]
| [[#SPI|spidev 4.0 Chip Select]] / [[#GPIO|GPIO Bank 5 IO 11]]
|-
|-
| 7
| 7
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 4]] / [[#UARTs|ttyS14 RX]]
| [[#GPIO|GPIO Bank 5 IO 4]] / [[#UARTs|ttyS14 RX]]
|-
|-
| 8
| 8
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 5]]
| [[#GPIO|GPIO Bank 5 IO 5]]
|-
|-
| 9
| 9
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 6]] / [[#UARTs|ttyS15 TX]]
| [[#GPIO|GPIO Bank 5 IO 6]] / [[#UARTs|ttyS15 TX]]
|-
|-
| 10
| 10
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#SPI|spidev 4.0 MISO]] / [[#GPIO|GPIO Bank 5 IO 10]] <ref>This pin is input only even when in the GPIO mode</ref>
| [[#SPI|spidev 4.0 MISO]] / [[#GPIO|GPIO Bank 5 IO 10]] <ref>This pin is input only even when in the GPIO mode</ref>
|-
|-
| 11
| 11
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 7]] / [[#UARTs|ttyS15 RX]]
| [[#GPIO|GPIO Bank 5 IO 7]] / [[#UARTs|ttyS15 RX]]
|-
|-
| 12
| 12
| [[#IO specifications|FPGA 3.3-V LVTTL]]
| [[#SPI|spidev 4.0 MOSI]] / [[#GPIO|GPIO Bank 5 IO 15]]
| [[#SPI|spidev 4.0 MOSI]] / [[#GPIO|GPIO Bank 5 IO 15]]
|-
|-
| 13
| 13
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 8]] / [[#UARTs|ttyS14 TXEN]]
| [[#GPIO|GPIO Bank 5 IO 8]] / [[#UARTs|ttyS14 TXEN]]
|-
|-
| 14
| 14
| [[#IO specifications|FPGA 3.3-V LVTTL]]
| [[#SPI|spidev 4.0 CLK]] / [[#GPIO|GPIO Bank 5 IO 14]]
| [[#SPI|spidev 4.0 CLK]] / [[#GPIO|GPIO Bank 5 IO 14]]
|-
|-
| 15
| 15
| [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]]
| [[#GPIO|GPIO Bank 5 IO 9]] / [[#UARTs|ttyS15 TXEN]]
| [[#GPIO|GPIO Bank 5 IO 9]] / [[#UARTs|ttyS15 TXEN]]
|-
|-
| 16
| 16
|
| [[#Board Rails|3.3V]]
| [[#Board Rails|3.3V]]
|}
|}

Revision as of 15:56, 22 September 2023

The DIO header is a 0.1" pitch 2x8 header including SPI and GPIO. All pins on this header are 5V tolerant except SPI output pins. All of these DIO includes pullups.

Signals Pin Layout
Pin IO Type Signal
1 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 1
2 GND
3 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 2
4 Open drain. High drives ground, low is tristate. Current Sink Output Bank 0 IO 30
5 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 3 / ttyS14 TX
6 FPGA 3.3-V LVTTL spidev 4.0 Chip Select / GPIO Bank 5 IO 11
7 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 4 / ttyS14 RX
8 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 5
9 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 6 / ttyS15 TX
10 FPGA 3.3-V LVTTL+QS3861 spidev 4.0 MISO / GPIO Bank 5 IO 10 [1]
11 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 7 / ttyS15 RX
12 FPGA 3.3-V LVTTL spidev 4.0 MOSI / GPIO Bank 5 IO 15
13 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 8 / ttyS14 TXEN
14 FPGA 3.3-V LVTTL spidev 4.0 CLK / GPIO Bank 5 IO 14
15 FPGA 3.3-V LVTTL+QS3861 GPIO Bank 5 IO 9 / ttyS15 TXEN
16 3.3V

TS-7250-V3-DIO Header.svg

  1. ↑ This pin is input only even when in the GPIO mode
KPAD.jpg

To use the SPI pins on this header as GPIO instead, disable SPI by changing the FPGA Syscon 0x08 bit 10: 

​tshwctl -a 0x8 --poke32 0x400

The DIO header is designed to provide compatibility with the KPAD accessory. This is a 4x4 numerical keypad. This is supported in userspace with the keypad.c source code, or the "keypad" utility which is included in the shiping image.

This debounces presses to 50ms, and does not repeat when numbers are held. This will output a string containing the key that is pressed. Eg: 

root@tsimx6:~# keypad
1
UP
DOWN
2ND
ENTER
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