TS-7250-V3 FPGA PWM: Difference between revisions
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(Created page with "The TS-7250-V3 includes a PWM core that supports 10-bit duty/period, a 79.2mhz input clock, and a /1 through /19 divider. Linux supports this API through the /sys/ interface....") |
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If using one of these frequencies, the full 10 bits of duty cycle are available. | |||
This core is located at 0x500001a8. | |||
{| class=wikitable: | |||
|- | |||
! Offset | |||
! Bits | |||
! Description | |||
|- | |||
| rowspan=3 | 0x0 | |||
| 15:2 | |||
| Reserved | |||
|- | |||
| 1 | |||
| Inversed (0 = idle high, duty cycle low), (1 = idle low, duty cycle high) | |||
|- | |||
| 0 | |||
| Enabled | |||
|- | |||
| rowspan=2 | 0x2 | |||
| 15:10 | |||
| Reserved | |||
|- | |||
| 9:0 | |||
| Period | |||
|- | |||
| rowspan=2 | 0x4 | |||
| 15:10 | |||
| Reserved | |||
|- | |||
| 9:0 | |||
| Duty Cycle | |||
|- | |||
| rowspan=2 | 0x4 | |||
| 15:10 | |||
| Reserved | |||
|- | |||
| 4:0 | |||
| div (Clock frequency = 79200000 / (2^div)) | |||
|} | |} |
Revision as of 11:50, 4 October 2021
The TS-7250-V3 includes a PWM core that supports 10-bit duty/period, a 79.2mhz input clock, and a /1 through /19 divider.
Linux supports this API through the /sys/ interface.
# Export PWM channel 0
echo 0 > /sys/class/pwm/pwmchip0/export
# Set Period ns
echo 0 > /sys/class/pwm/pwmchip0/export
The Linux PWM API will attempt to arrive at the exact period at the cost of the duty cycle resolution. For the most expressive duty cycle, target a frequency that is an exact division of the input clock.
Divisor | Frequency (hz) | Max Period (ns) |
---|---|---|
1 | 3960000 | 252.53 |
2 | 1980000 | 505.05 |
3 | 990000 | 1010.10 |
4 | 495000 | 2020.20 |
5 | 247500 | 4040.40 |
6 | 123750 | 8080.81 |
7 | 61875 | 16161.62 |
8 | 30937.50 | 32323.23 |
9 | 15468.75 | 64646.46 |
10 | 7734.38 | 129292.93 |
11 | 3867.19 | 258585.86 |
12 | 1933.59 | 517171.72 |
13 | 966.80 | 1034343.43 |
14 | 483.40 | 2068686.87 |
15 | 241.70 | 4137373.74 |
16 | 120.85 | 8274747.47 |
17 | 60.42 | 16549494.95 |
18 | 30.21 | 33098989.90 |
19 | 15.11 | 66197979.80 |
If using one of these frequencies, the full 10 bits of duty cycle are available.
This core is located at 0x500001a8.
Offset | Bits | Description |
---|---|---|
0x0 | 15:2 | Reserved |
1 | Inversed (0 = idle high, duty cycle low), (1 = idle low, duty cycle high) | |
0 | Enabled | |
0x2 | 15:10 | Reserved |
9:0 | Period | |
0x4 | 15:10 | Reserved |
9:0 | Duty Cycle | |
0x4 | 15:10 | Reserved |
4:0 | div (Clock frequency = 79200000 / (2^div)) |