TS-7250-V3 FPGA PWM: Difference between revisions
From embeddedTS Manuals
No edit summary |
No edit summary |
||
Line 17: | Line 17: | ||
! Frequency (hz) | ! Frequency (hz) | ||
! Max Period (ns) | ! Max Period (ns) | ||
|- | |||
| 0 | |||
| 79200000.00 | |||
| 12917 | |||
|- | |- | ||
| 1 | | 1 | ||
| 3960000 | | 3960000 | ||
| | | 25833 | ||
|- | |- | ||
| 2 | | 2 | ||
| 1980000 | | 1980000 | ||
| | | 51667 | ||
|- | |- | ||
| 3 | | 3 | ||
| 990000 | | 990000 | ||
| | | 103333 | ||
|- | |- | ||
| 4 | | 4 | ||
| 495000 | | 495000 | ||
| | | 206667 | ||
|- | |- | ||
| 5 | | 5 | ||
| 247500 | | 247500 | ||
| | | 413333 | ||
|- | |- | ||
| 6 | | 6 | ||
| 123750 | | 123750 | ||
| | | 826667 | ||
|- | |- | ||
| 7 | | 7 | ||
| 61875 | | 61875 | ||
| | | 1653333 | ||
|- | |- | ||
| 8 | | 8 | ||
| 30937.50 | | 30937.50 | ||
| | | 3306667 | ||
|- | |- | ||
| 9 | | 9 | ||
| 15468.75 | | 15468.75 | ||
| | | 6613333 | ||
|- | |- | ||
| 10 | | 10 | ||
| 7734.38 | | 7734.38 | ||
| | | 13226667 | ||
|- | |- | ||
| 11 | | 11 | ||
| 3867.19 | | 3867.19 | ||
| | | 26453333 | ||
|- | |- | ||
| 12 | | 12 | ||
| 1933.59 | | 1933.59 | ||
| | | 52906667 | ||
|- | |- | ||
| 13 | | 13 | ||
| 966.80 | | 966.80 | ||
| | | 105813333 | ||
|- | |- | ||
| 14 | | 14 | ||
| 483.40 | | 483.40 | ||
| | | 211626667 | ||
|- | |- | ||
| 15 | | 15 | ||
| 241.70 | | 241.70 | ||
| | | 423253333 | ||
|- | |- | ||
| 16 | | 16 | ||
| 120.85 | | 120.85 | ||
| | | 846506667 | ||
|- | |- | ||
| 17 | | 17 | ||
| 60.42 | | 60.42 | ||
| | | 1693013333 | ||
|- | |- | ||
| 18 | | 18 | ||
| 30.21 | | 30.21 | ||
| | | 3386026667 | ||
|- | |- | ||
| 19 | | 19 | ||
| 15.11 | | 15.11 | ||
| | | 6772053333 | ||
|} | |} | ||
Revision as of 09:49, 5 October 2021
The TS-7250-V3 includes a PWM core that supports 10-bit duty/period, a 79.2mhz input clock, and a /1 through /19 divider.
Linux supports this API through the /sys/ interface.
# Export PWM channel 0
echo 0 > /sys/class/pwm/pwmchip0/export
# Set Period ns
echo 0 > /sys/class/pwm/pwmchip0/export
The Linux PWM API will attempt to arrive at the exact period at the cost of the duty cycle resolution. For the most expressive duty cycle, target a frequency that is an exact division of the input clock.
Divisor | Frequency (hz) | Max Period (ns) |
---|---|---|
0 | 79200000.00 | 12917 |
1 | 3960000 | 25833 |
2 | 1980000 | 51667 |
3 | 990000 | 103333 |
4 | 495000 | 206667 |
5 | 247500 | 413333 |
6 | 123750 | 826667 |
7 | 61875 | 1653333 |
8 | 30937.50 | 3306667 |
9 | 15468.75 | 6613333 |
10 | 7734.38 | 13226667 |
11 | 3867.19 | 26453333 |
12 | 1933.59 | 52906667 |
13 | 966.80 | 105813333 |
14 | 483.40 | 211626667 |
15 | 241.70 | 423253333 |
16 | 120.85 | 846506667 |
17 | 60.42 | 1693013333 |
18 | 30.21 | 3386026667 |
19 | 15.11 | 6772053333 |
If using one of these frequencies, the full 10 bits of duty cycle are available.
This core is located at 0x500001a8.
Offset | Bits | Description |
---|---|---|
0x0 | 15:2 | Reserved |
1 | Inversed (0 = idle high, duty cycle low), (1 = idle low, duty cycle high) | |
0 | Enabled | |
0x2 | 15:10 | Reserved |
9:0 | Period | |
0x4 | 15:10 | Reserved |
9:0 | Duty Cycle | |
0x6 | 15:10 | Reserved |
4:0 | div (Clock frequency = 79200000 / (2^div)) |