TS-7250-V3 FPGA PWM
From embeddedTS Manuals
The TS-7250-V3 includes a PWM core that supports 10-bit duty/period, a 79.2mhz input clock, and 20 values of input clock shift.
Linux supports this API through the /sys/ interface.
# Export PWM channel 0
echo 0 > /sys/class/pwm/pwmchip0/export
# Set Period ns
echo 0 > /sys/class/pwm/pwmchip0/export
The Linux PWM API will attempt to arrive at the exact period at the cost of the duty cycle resolution. For the most expressive duty cycle, target a frequency that is an exact shift of the input clock. Linux's API maxes out the max period/duty as 4294967295ns
| Divisor | Frequency (hz) | Max Period (ns) |
|---|---|---|
| 0 | 79200000 | 12917 |
| 1 | 3960000 | 25833 |
| 2 | 1980000 | 51667 |
| 3 | 990000 | 103333 |
| 4 | 495000 | 206667 |
| 5 | 247500 | 413333 |
| 6 | 123750 | 826667 |
| 7 | 61875 | 1653333 |
| 8 | 30937.50 | 3306667 |
| 9 | 15468.75 | 6613333 |
| 10 | 7734.38 | 13226795 |
| 11 | 3867.19 | 26453932 |
| 12 | 1933.59 | 52909232 |
| 13 | 966.80 | 105823937 |
| 14 | 483.40 | 211669770 |
| 15 | 241.70 | 423427152 |
| 16 | 120.85 | 846854305 |
| 17 | 60.42 | 1693708609 |
| 18 | 30.21 | 3387417219 |
| 19 | 15.11 | 6774834437 |
If period is set to one of these values, the full 10 bits of duty cycle is available. Past that, the Linux API will use the closest available value.
This core is located at 0x500001a8.
| Offset | Bits | Description |
|---|---|---|
| 0x0 | 15:2 | Reserved |
| 1 | Inversed (0 = idle high, duty cycle low), (1 = idle low, duty cycle high) | |
| 0 | Enabled | |
| 0x2 | 15:10 | Reserved |
| 9:0 | Period | |
| 0x4 | 15:10 | Reserved |
| 9:0 | Duty Cycle | |
| 0x6 | 15:10 | Reserved |
| 4:0 | shift (Clock frequency = 79200000 / (1 >> shift)) |