TS-7250-V3 IO Ranges: Difference between revisions
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! Source Current | ! Source Current | ||
! Sink Current | ! Sink Current | ||
! VIL | |||
! VIH | |||
|- | |||
| CPU 3.3V | |||
| 3.3V | |||
| 3.6V | |||
| | |||
| | |||
| 2.31 | |||
| 0.99 | |||
|- | |||
| CPU 3.3V+QS3861 | |||
| 5V | |||
| 7V | |||
| | |||
| | |||
| | |||
| | |||
|- | |- | ||
| FPGA 3.3-V LVTTL | | FPGA 3.3-V LVTTL | ||
| Line 12: | Line 30: | ||
| 6mA | | 6mA | ||
| 6mA | | 6mA | ||
| | |||
| | |||
|- | |- | ||
| FPGA 3.3-V LVTTL+QS3861 | | FPGA 3.3-V LVTTL+QS3861 | ||
| Line 18: | Line 38: | ||
| 6mA | | 6mA | ||
| 6mA | | 6mA | ||
| | |||
| | |||
|- | |||
| PCA9555 | |||
| 5.3V | |||
| 6V | |||
| 25mA <ref>"Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a | |||
maximum current of 100 mA for a device total of 200 mA. The total current sourced by all I/Os must be limited to 160 mA</ref> | |||
| 8-24mA | |||
| 0.3V | |||
| 2.31V | |||
|} | |} | ||
<References /> | <References /> | ||
Latest revision as of 17:58, 22 September 2023
| IO Type | Voltage max | Absolute max | Source Current | Sink Current | VIL | VIH |
|---|---|---|---|---|---|---|
| CPU 3.3V | 3.3V | 3.6V | 2.31 | 0.99 | ||
| CPU 3.3V+QS3861 | 5V | 7V | ||||
| FPGA 3.3-V LVTTL | 3.3V | 3.6V | 6mA | 6mA | ||
| FPGA 3.3-V LVTTL+QS3861 | 5V | 7V | 6mA | 6mA | ||
| PCA9555 | 5.3V | 6V | 25mA [1] | 8-24mA | 0.3V | 2.31V |
- ↑ "Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. The total current sourced by all I/Os must be limited to 160 mA