TS-7250-V3 PC104 Header: Difference between revisions
From embeddedTS Manuals
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Line 35: | Line 35: | ||
|- | |- | ||
| B28 | | B28 | ||
| [[#GPIO|Bank 6 IO 1]] | | [[#GPIO|Bank 6 IO 1]]/[[#PC104_Bus|TS mode DAT15]] | ||
| A28 | | A28 | ||
| [[#PC104_Bus|ISA_ADD_03]]/[[#GPIO|Bank 9 IO 3]] | | [[#PC104_Bus|ISA_ADD_03]]/[[#GPIO|Bank 9 IO 3]] | ||
Line 44: | Line 44: | ||
|- | |- | ||
| B27 | | B27 | ||
| [[#GPIO|Bank 6 IO 2]] | | [[#GPIO|Bank 6 IO 2]]/[[#PC104_Bus|TS mode DAT14]] | ||
| A27 | | A27 | ||
| [[#PC104_Bus|ISA_ADD_04]]/[[#GPIO|Bank 9 IO 4]] | | [[#PC104_Bus|ISA_ADD_04]]/[[#GPIO|Bank 9 IO 4]] | ||
Line 53: | Line 53: | ||
|- | |- | ||
| B26 | | B26 | ||
| [[#GPIO|Bank 6 IO 10]] | | [[#GPIO|Bank 6 IO 10]]/[[#PC104_Bus|TS mode DAT13]] | ||
| A26 | | A26 | ||
| [[#PC104_Bus|ISA_ADD_05]]/[[#GPIO|Bank 9 IO 5]] | | [[#PC104_Bus|ISA_ADD_05]]/[[#GPIO|Bank 9 IO 5]] | ||
Line 62: | Line 62: | ||
|- | |- | ||
| B25 | | B25 | ||
| [[#FPGA_IRQs|FPGA IRQ 13]] | | [[#FPGA_IRQs|FPGA IRQ 13]]/[[#PC104_Bus|TS mode DAT11]] | ||
| A25 | | A25 | ||
| [[#PC104_Bus|ISA_ADD_06]]/[[#GPIO|Bank 9 IO 6]] | | [[#PC104_Bus|ISA_ADD_06]]/[[#GPIO|Bank 9 IO 6]] | ||
Line 107: | Line 107: | ||
|- | |- | ||
| B20 | | B20 | ||
| | | [[#PC104_Bus|TS mode DAT12]] | ||
| A20 | | A20 | ||
| [[#PC104_Bus|ISA_ADD_11]]/[[#GPIO|Bank 9 IO 11]] | | [[#PC104_Bus|ISA_ADD_11]]/[[#GPIO|Bank 9 IO 11]] | ||
Line 125: | Line 125: | ||
|- | |- | ||
| B18 | | B18 | ||
| [[#GPIO|Bank 6 IO 7]] | | [[#GPIO|Bank 6 IO 7]]/[[#PC104_Bus|TS mode DAT10]] | ||
| A18 | | A18 | ||
| [[#PC104_Bus|ISA_ADD_13]]/[[#GPIO|Bank 9 IO 13]] | | [[#PC104_Bus|ISA_ADD_13]]/[[#GPIO|Bank 9 IO 13]] | ||
Line 134: | Line 134: | ||
|- | |- | ||
| B17 | | B17 | ||
| [[#GPIO|Bank 6 IO 8]] | | [[#GPIO|Bank 6 IO 8]]/[[#PC104_Bus|TS mode DAT9]] | ||
| A17 | | A17 | ||
| [[#PC104_Bus|ISA_ADD_14]]/[[#GPIO|Bank 9 IO 14]] | | [[#PC104_Bus|ISA_ADD_14]]/[[#GPIO|Bank 9 IO 14]] | ||
Line 236: | Line 236: | ||
|- | |- | ||
| B04 | | B04 | ||
| [[#FPGA_IRQs|FPGA IRQ 17]] | | [[#FPGA_IRQs|FPGA IRQ 17]]/[[#PC104_Bus|TS mode DAT8]] | ||
| A04 | | A04 | ||
| [[#PC104_Bus|ISA_DAT_02]]/[[#GPIO|Bank 8 IO 2]] | | [[#PC104_Bus|ISA_DAT_02]]/[[#GPIO|Bank 8 IO 2]] |
Revision as of 11:09, 16 December 2021
The PC104 connector consists of four rows of pins labelled A-D. This header implements the #PC104 Bus, and optionally most pins can be GPIO.
- ↑ Outputs a continuous 14.318180 MHz clock
- ↑ 2.0 2.1 2.2 Powering the system from PC104 5V prevents the Board's low power sleep mode from functioning.
- ↑ This pin can be used to supply power to the board through the switching regulator.
- ↑ This is automatically pulsed on startup by the ts-pc104 driver as ISA_RESET