TS-7250-V3 PC104 bus
The TS-7250-V3 includes an ISA bus for compatibility with PC104 peripherals. ARM itself has not traditionally had an ISA bus as part of its architecture, so this behaves differently than on X86 where ISA is typically used. The FPGA has two memory windows, one for the kernel, and one for userspace. The FPGA will handle locking between these two accesses. In the kernel the driver will handle locking between different kernel accesses to this bus. Under userspace this is the user's responsibility.
| Memory Window Address | Description |
|---|---|
| 0x50004050 | Used by the kernel only |
| 0x50004054 | Used by userspace only. |
In the Linux kernel, see the header at include/linux/tspc104_bus.h for various bus accesses.
In most cases users should use our abstraction to PC104, or the existing kernel drivers, but the memory window at either location follows this register format:
| Bits | Description |
|---|---|
| 31 | Busy/Go [1] |
| 30 | 1 = IO, 0 = MEM [2] |
| 29 | 1 = 8-bit, 0 = 16-bit |
| 28 | 1 = read cycle, 0 = write cycle |
| 27 | 0 = standard pinout, 1 = TS Pinout [3] |
| 26:0 | Address or Data <ref>Accepts a written addr when BUSY/GO = 0. This is data on a write when Busy/GO=1, or on a read after BUSY/GO reads 0 after being written to 1.<ref> |
- ↑ On read, a 1 indicates the existing transaction is already busy. A 0 indicates it is available. If written to 0 then bits 26:0 specify address. If written to 1 this starts the bus cycle.
- ↑ Cycle type indicates if we use IOW/IOR pins, or MEMR/MEMW.
- ↑ The TS pinout is used on some platforms to remove the need for the 40-pin connnector while still supporting 16-bit peripherals. This does not affect 8-bit accesses. When enabled this uses these pins for the upper 16-bit.
PC104 pin Data bit B4 8 B17 9 B18 10 B25 11 B20 12 B26 13 B14 14 B28 15