TS-7400-V2 Migration: Difference between revisions

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(Created page with "=Pin-by-pin comparison= ==Upper header pin-out (26-pin)== {| class="wikitable sortable" ! ! colspan=2 | TS-7400 ! colspan=2 | TS-7400_V2 |- ! Pin # ! Name ! Function ! Name...")
 
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==Upper header pin-out (26-pin)==
==Upper header pin-out (26-pin)==
 
{| class="zebra wikitable sortable"
{| class="wikitable sortable"
!  
!  
! colspan=2 | TS-7400
! colspan=2 | TS-7400
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| SD_BOOT#
| SD_BOOT#
| Boot mode pin (SD or NAND)
| Boot mode pin (SD or NAND)
|-
| 3
| GND
| Ground
| GND
| Ground
|-
| 4
| TDI
| TS Production Reserved
| GND
| Ground
|-
| 5
| BLAST_BOOT#
| input, low will hijack CPU SPI bootstrap
| FPGA_DIO_0
| DIO (Will change in future hardware rev)
|-
| 6
| TCK
| TS Production Reserved
| I2C Clk
| I2C Clock pin
|-
| 7
| UART0_TXD
| ep9302 UART #0 output (/dev/ttyAM0 in Linux)
| DEBUG_TXD
| i.MX286 Debug UART TX /dev/ttyAM0
|-
| 8
| UART0_RXD
| ep9302 UART #0 input (/dev/ttyAM0 in Linux)
| DEBUG_RXD
| i.MX286 Debug UART RX /dev/ttyAM0
|-
| 9
| SPI_MISO
| SPI Master-in, slave-out
| SPI_MISO
| SPI Master-in, slave-out
|-
| 10
| 3.3V
| 3.3V TS-7400 regulator output (or input, if U6 regulator is not populated)
| 3.3V
| 3.3V Aux output
|-
| 11
| BLAST_EE_CS#
| Chip-select for SPI boot hijack EEPROM
| FPGA_DIO_1
| DIO (Will change in future hardware rev)
|-
| 12
| SPI_MOSI
| SPI Master-out, slave-in
| SPI_MOSI
| SPI Master-out, slave-in
|-
| 13
| FLASH_CS#
| Chip-select used for 2 megabyte SPI flash on TS-9441 (used by TS-SPIBOOT boot program)
| FPGA_DIO_2
| DIO (Will change in future hardware rev)
|-
| 14
| SPI_CLK
| SPI clock output
| SPI_CLK
| SPI clock output
|-
| 15
| 5V
| 5V regulated power input/output
| 5V
| 5V regulated power input
|-
| 16
| EXT_RESET#
| External reset input, low triggers board reset
| HARD_REBOOT#
| External reset input, low triggers board reset
|-
| 17
| BLAST_PRESENT#
| Boot hijacker present input
| FPGA_DIO_3
| DIO (Will change in future hardware rev)
|-
| 18
| GND
| Ground
| GND
| Ground
|-
| 19
| PORTB_4
| CPU connected GPIO pin, 5V tolerant with external series resistor.
| DIO_19
| CPU DIO
|-
| 20
| GND
| Ground
| GND
| Ground
|-
| 21
| EN_5V
| Switching power supply enable input, open-drain, pull low to disable 5V switcher
| FPGA_DIO_4
| DIO (Will change in future hardware rev)
|-
| 22
| EP_USB+
| EP93xx CPU USB port data signal
| USB_OTG_P
| i.MX286 USB OTG port data signal
|-
| 23
| FIL_VIN
| Reserved
| FPGA_DIO_5
| DIO (Will change in future hardware rev)
|-
| 24
| EP_USB-
| EP93xx CPU USB port data signal
| USB_OTG_M
| i.MX286 USB OTG port data signal
|-
| 25
| PORTB_7
| CPU connected GPIO pin, 6.49k pull-down and 1k series resistors. 5V tolerant.
| DIO_25
| CPU DIO
|-
| 26
| USB_5V
| USB 5V power
| USB_SW_5V
| Switched USB 5V power
|}
|}

Revision as of 12:42, 17 September 2013

Pin-by-pin comparison

Upper header pin-out (26-pin)

TS-7400 TS-7400_V2
Pin # Name Function Name Function
1 TDO TS Production Reserved I2C Dat I2C Data pin
2 TMS TS Production Reserved SD_BOOT# Boot mode pin (SD or NAND)
3 GND Ground GND Ground
4 TDI TS Production Reserved GND Ground
5 BLAST_BOOT# input, low will hijack CPU SPI bootstrap FPGA_DIO_0 DIO (Will change in future hardware rev)
6 TCK TS Production Reserved I2C Clk I2C Clock pin
7 UART0_TXD ep9302 UART #0 output (/dev/ttyAM0 in Linux) DEBUG_TXD i.MX286 Debug UART TX /dev/ttyAM0
8 UART0_RXD ep9302 UART #0 input (/dev/ttyAM0 in Linux) DEBUG_RXD i.MX286 Debug UART RX /dev/ttyAM0
9 SPI_MISO SPI Master-in, slave-out SPI_MISO SPI Master-in, slave-out
10 3.3V 3.3V TS-7400 regulator output (or input, if U6 regulator is not populated) 3.3V 3.3V Aux output
11 BLAST_EE_CS# Chip-select for SPI boot hijack EEPROM FPGA_DIO_1 DIO (Will change in future hardware rev)
12 SPI_MOSI SPI Master-out, slave-in SPI_MOSI SPI Master-out, slave-in
13 FLASH_CS# Chip-select used for 2 megabyte SPI flash on TS-9441 (used by TS-SPIBOOT boot program) FPGA_DIO_2 DIO (Will change in future hardware rev)
14 SPI_CLK SPI clock output SPI_CLK SPI clock output
15 5V 5V regulated power input/output 5V 5V regulated power input
16 EXT_RESET# External reset input, low triggers board reset HARD_REBOOT# External reset input, low triggers board reset
17 BLAST_PRESENT# Boot hijacker present input FPGA_DIO_3 DIO (Will change in future hardware rev)
18 GND Ground GND Ground
19 PORTB_4 CPU connected GPIO pin, 5V tolerant with external series resistor. DIO_19 CPU DIO
20 GND Ground GND Ground
21 EN_5V Switching power supply enable input, open-drain, pull low to disable 5V switcher FPGA_DIO_4 DIO (Will change in future hardware rev)
22 EP_USB+ EP93xx CPU USB port data signal USB_OTG_P i.MX286 USB OTG port data signal
23 FIL_VIN Reserved FPGA_DIO_5 DIO (Will change in future hardware rev)
24 EP_USB- EP93xx CPU USB port data signal USB_OTG_M i.MX286 USB OTG port data signal
25 PORTB_7 CPU connected GPIO pin, 6.49k pull-down and 1k series resistors. 5V tolerant. DIO_25 CPU DIO
26 USB_5V USB 5V power USB_SW_5V Switched USB 5V power
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