TS-7400-V2 Migration: Difference between revisions
From embeddedTS Manuals
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Line 51: | Line 51: | ||
| 7 | | 7 | ||
| UART0_TXD | | UART0_TXD | ||
| | | UART0 TXD ttyAM0 | ||
| DEBUG_TXD | | DEBUG_TXD | ||
| | | Debug UART TXD ttyAM0 | ||
|- | |- | ||
| 8 | | 8 | ||
| UART0_RXD | | UART0_RXD | ||
| | | UART0 RXD ttyAM0 | ||
| DEBUG_RXD | | DEBUG_RXD | ||
| | | Debug UART RX ttyAM0 | ||
|- | |- | ||
| 9 | | 9 | ||
Line 69: | Line 69: | ||
| 10 | | 10 | ||
| 3.3V | | 3.3V | ||
| 3.3V | | 3.3V Output | ||
| 3.3V | | 3.3V | ||
| 3.3V | | 3.3V Output | ||
|- | |- | ||
| 11 | | 11 | ||
Line 87: | Line 87: | ||
| 13 | | 13 | ||
| FLASH_CS# | | FLASH_CS# | ||
| Chip | | Chip select for SPI flash on TS-9441 | ||
| FPGA_DIO_2 | | FPGA_DIO_2 | ||
| DIO (Will change in future hardware rev) | | DIO (Will change in future hardware rev) | ||
Line 99: | Line 99: | ||
| 15 | | 15 | ||
| 5V | | 5V | ||
| 5V regulated power input | | 5V regulated power input | ||
| 5V | | 5V | ||
| 5V regulated power input | | 5V regulated power input | ||
Line 123: | Line 123: | ||
| 19 | | 19 | ||
| PORTB_4 | | PORTB_4 | ||
| CPU | | CPU DIO | ||
| DIO_19 | | DIO_19 | ||
| CPU DIO | | CPU DIO | ||
Line 135: | Line 135: | ||
| 21 | | 21 | ||
| EN_5V | | EN_5V | ||
| Switching power supply enable | | Switching power supply enable, open-drain | ||
| FPGA_DIO_4 | | FPGA_DIO_4 | ||
| DIO (Will change in future hardware rev) | | DIO (Will change in future hardware rev) | ||
Line 159: | Line 159: | ||
| 25 | | 25 | ||
| PORTB_7 | | PORTB_7 | ||
| CPU connected GPIO pin | | CPU connected GPIO pin | ||
| DIO_25 | | DIO_25 | ||
| CPU DIO | | CPU DIO | ||
Line 168: | Line 168: | ||
| USB_SW_5V | | USB_SW_5V | ||
| Switched USB 5V power | | Switched USB 5V power | ||
|} | |||
==Lower header pin-put (40-pin)== | |||
{| class="zebra wikitable sortable" | |||
! | |||
! colspan=2 | TS-7400 | |||
! colspan=2 | TS-7400_V2 | |||
|- | |||
! Pin # | |||
! Name | |||
! Function | |||
! Name | |||
! Function | |||
|- | |||
| 1 | |||
| DIO_00 | |||
| GPIO0 or GPBUS AD0 | |||
| DIO_00 | |||
| CPU DIO | |||
|- | |||
| 2 | |||
| 3.3V | |||
| 3.3V Output | |||
| 3.3V | |||
| 3.3V Output | |||
|- | |||
| 3 | |||
| DIO_01 | |||
| GPIO1 or GPBUS AD1 | |||
| DIO_01 | |||
| CPU DIO | |||
|- | |||
| 4 | |||
| DIO_02 | |||
| GPIO2 or GPBUS AD2 | |||
| DIO_02 | |||
| CPU DIO | |||
|- | |||
| 5 | |||
| DIO_03 | |||
| GPIO3 or GPBUS AD3 | |||
| DIO_03 | |||
| CPU DIO | |||
|- | |||
| 6 | |||
| DIO_04 | |||
| GPIO4 or GPBUS AD4 | |||
| DIO_04 | |||
| CPU DIO | |||
|- | |||
| 7 | |||
| DIO_05 | |||
| GPIO5 or GPBUS AD5 | |||
| DIO_05 | |||
| CPU DIO | |||
|- | |||
| 8 | |||
| DIO_06 | |||
| GPIO6 or GPBUS AD6 | |||
| DIO_06 | |||
| CPU DIO | |||
|- | |||
| 9 | |||
| DIO_07 | |||
| GPIO7 or GPBUS AD7 | |||
| DIO_07 | |||
| CPU DIO | |||
|- | |||
| 10 | |||
| DIO_08 | |||
| GPIO8 or GPBUS ALE | |||
| DIO_08 | |||
| CPU DIO | |||
|- | |||
| 11 | |||
| DIO_09 | |||
| GPIO9 or GPBUS RD | |||
| DIO_09 | |||
| CPU DIO | |||
|- | |||
| 12 | |||
| GND | |||
| Ground | |||
| GND | |||
| Ground | |||
|- | |||
| 13 | |||
| DIO_10 | |||
| GPIO10 or GPBUS WR | |||
| CAN_RX0 | |||
| CAN RX0 or DIO | |||
|- | |||
| 14 | |||
| DIO_11 | |||
| GPIO11 or GPBUS IRQ | |||
| CAN_RX1 | |||
| CAN RX1 or DIO | |||
|- | |||
| 15 | |||
| DIO_15 | |||
| GPIO12 or GPBUS DRQ | |||
| CAN_TX0 | |||
| CAN TX0 or DIO | |||
|- | |||
| 16 | |||
| DIO_13 | |||
| GPIO13 or GPBUS 14.7456Mhz clock | |||
| CAN_TX1 | |||
| CAN TX1 or DIO | |||
|- | |||
| 17 | |||
| DIO_14 | |||
| GPIO14 | |||
| UART3_TXD | |||
| UART3 or DIO | |||
|- | |||
| 18 | |||
| 5V | |||
| 5V regulated power input/output | |||
| 5V | |||
| 5V regulated power input | |||
|- | |||
| 19 | |||
| DIO_15 | |||
| GPIO15 or UART2 TXEN ttyTS0 | |||
| DIO_15 | |||
| CPU DIO | |||
|- | |||
| 20 | |||
| DIO_16 | |||
| GPIO16 or UART2 RXD ttyTS0 | |||
| UART2_RXD | |||
| UART2 or DIO | |||
|- | |||
| 21 | |||
| DIO_17 | |||
| GPIO17 or UART2 TXD ttyTS0 | |||
| UART2_TXD | |||
| UART2 or DIO | |||
|- | |||
| 22 | |||
| DIO_18 | |||
| GPIO18 or UART0 TXD ttyAM0 | |||
| UART0_TXD | |||
| UART0 or DIO | |||
|- | |||
| 23 | |||
| DIO_19 | |||
| GPIO19 or UART0 RXD ttyAM0 | |||
| UART0_RXD | |||
| UART0 or DIO | |||
|- | |||
| 24 | |||
| UART1_RXD | |||
| UART1 RXD ttyAM1 | |||
| UART1_RXD | |||
| UART1 or DIO | |||
|- | |||
| 25 | |||
| UART1_TXD | |||
| UART1 TXD ttyAM1 | |||
| UART1_TXD | |||
| UART1 or DIO | |||
|- | |||
| 26 | |||
| 1.8V | |||
| 1.8V | |||
| UART3_RXD | |||
| UART3 or DIO | |||
|- | |||
| 27 | |||
| ADC0 | |||
| EP93xx ADC0 | |||
| ADC0 | |||
| i.MX286 LRADC0 | |||
|- | |||
| 28 | |||
| ADC1 | |||
| EP93xx ADC1 | |||
| ADC1 | |||
| i.MX286 LRADC1 | |||
|- | |||
| 29 | |||
| ADC2 | |||
| EP93xx ADC2 | |||
| ADC2 | |||
| i.MX286 LRADC2 | |||
|- | |||
| 30 | |||
| ADC3 | |||
| EP93xx ADC3 | |||
| ADC3 | |||
| i.MX283 LRADC3 | |||
|- | |||
| 31 | |||
| GND | |||
| Ground | |||
| GND | |||
| Ground | |||
|- | |||
| 32 | |||
| ABIT_CLK | |||
| EP93xx CPU AC97 | |||
| I2S_BIT_CLK | |||
| I2S Clock | |||
|- | |||
| 33 | |||
| ASDO | |||
| EP93xx CPU AC97 | |||
| I2S_TXD | |||
| I2S Data transmit | |||
|- | |||
| 34 | |||
| ASYNCH | |||
| EP93xx CPU AC97 | |||
| I2S_FRAME | |||
| I2S Frame | |||
|- | |||
| 35 | |||
| ARST# | |||
| EP93xx CPU AC97 | |||
| I2S_MCLK | |||
| I2S MCLK | |||
|- | |||
| 36 | |||
| ASDI | |||
| EP93xx CPU AC97 | |||
| I2S_RXD | |||
| I2S Data Receive | |||
|- | |||
| 37 | |||
| SSP_TX | |||
| EP93xx SPI/SSP/I2S signal | |||
| SPI_MOSI | |||
| SPI Master-out, slave-in | |||
|- | |||
| 38 | |||
| SSP_RX | |||
| EP93xx SPI/SSP/I2S signal | |||
| SPI_MISO | |||
| SPI Master-in, slave-out | |||
|- | |||
| 39 | |||
| SSP_FRM | |||
| EP93xx SPI/SSP/I2S signal | |||
| SPI_CS# | |||
| SPI Chip select | |||
|- | |||
| 40 | |||
| SSP_CLK | |||
| EP93xx SPI/SSP/I2S signal | |||
| SPI_CLK | |||
| SPI Clock | |||
|} | |} |
Revision as of 14:17, 17 September 2013
Pin-by-pin comparison
Upper header pin-out (26-pin)
TS-7400 | TS-7400_V2 | |||
---|---|---|---|---|
Pin # | Name | Function | Name | Function |
1 | TDO | TS Production Reserved | I2C Dat | I2C Data pin |
2 | TMS | TS Production Reserved | SD_BOOT# | Boot mode pin (SD or NAND) |
3 | GND | Ground | GND | Ground |
4 | TDI | TS Production Reserved | GND | Ground |
5 | BLAST_BOOT# | input, low will hijack CPU SPI bootstrap | FPGA_DIO_0 | DIO (Will change in future hardware rev) |
6 | TCK | TS Production Reserved | I2C Clk | I2C Clock pin |
7 | UART0_TXD | UART0 TXD ttyAM0 | DEBUG_TXD | Debug UART TXD ttyAM0 |
8 | UART0_RXD | UART0 RXD ttyAM0 | DEBUG_RXD | Debug UART RX ttyAM0 |
9 | SPI_MISO | SPI Master-in, slave-out | SPI_MISO | SPI Master-in, slave-out |
10 | 3.3V | 3.3V Output | 3.3V | 3.3V Output |
11 | BLAST_EE_CS# | Chip-select for SPI boot hijack EEPROM | FPGA_DIO_1 | DIO (Will change in future hardware rev) |
12 | SPI_MOSI | SPI Master-out, slave-in | SPI_MOSI | SPI Master-out, slave-in |
13 | FLASH_CS# | Chip select for SPI flash on TS-9441 | FPGA_DIO_2 | DIO (Will change in future hardware rev) |
14 | SPI_CLK | SPI clock output | SPI_CLK | SPI clock output |
15 | 5V | 5V regulated power input | 5V | 5V regulated power input |
16 | EXT_RESET# | External reset input, low triggers board reset | HARD_REBOOT# | External reset input, low triggers board reset |
17 | BLAST_PRESENT# | Boot hijacker present input | FPGA_DIO_3 | DIO (Will change in future hardware rev) |
18 | GND | Ground | GND | Ground |
19 | PORTB_4 | CPU DIO | DIO_19 | CPU DIO |
20 | GND | Ground | GND | Ground |
21 | EN_5V | Switching power supply enable, open-drain | FPGA_DIO_4 | DIO (Will change in future hardware rev) |
22 | EP_USB+ | EP93xx CPU USB port data signal | USB_OTG_P | i.MX286 USB OTG port data signal |
23 | FIL_VIN | Reserved | FPGA_DIO_5 | DIO (Will change in future hardware rev) |
24 | EP_USB- | EP93xx CPU USB port data signal | USB_OTG_M | i.MX286 USB OTG port data signal |
25 | PORTB_7 | CPU connected GPIO pin | DIO_25 | CPU DIO |
26 | USB_5V | USB 5V power | USB_SW_5V | Switched USB 5V power |
Lower header pin-put (40-pin)
TS-7400 | TS-7400_V2 | |||
---|---|---|---|---|
Pin # | Name | Function | Name | Function |
1 | DIO_00 | GPIO0 or GPBUS AD0 | DIO_00 | CPU DIO |
2 | 3.3V | 3.3V Output | 3.3V | 3.3V Output |
3 | DIO_01 | GPIO1 or GPBUS AD1 | DIO_01 | CPU DIO |
4 | DIO_02 | GPIO2 or GPBUS AD2 | DIO_02 | CPU DIO |
5 | DIO_03 | GPIO3 or GPBUS AD3 | DIO_03 | CPU DIO |
6 | DIO_04 | GPIO4 or GPBUS AD4 | DIO_04 | CPU DIO |
7 | DIO_05 | GPIO5 or GPBUS AD5 | DIO_05 | CPU DIO |
8 | DIO_06 | GPIO6 or GPBUS AD6 | DIO_06 | CPU DIO |
9 | DIO_07 | GPIO7 or GPBUS AD7 | DIO_07 | CPU DIO |
10 | DIO_08 | GPIO8 or GPBUS ALE | DIO_08 | CPU DIO |
11 | DIO_09 | GPIO9 or GPBUS RD | DIO_09 | CPU DIO |
12 | GND | Ground | GND | Ground |
13 | DIO_10 | GPIO10 or GPBUS WR | CAN_RX0 | CAN RX0 or DIO |
14 | DIO_11 | GPIO11 or GPBUS IRQ | CAN_RX1 | CAN RX1 or DIO |
15 | DIO_15 | GPIO12 or GPBUS DRQ | CAN_TX0 | CAN TX0 or DIO |
16 | DIO_13 | GPIO13 or GPBUS 14.7456Mhz clock | CAN_TX1 | CAN TX1 or DIO |
17 | DIO_14 | GPIO14 | UART3_TXD | UART3 or DIO |
18 | 5V | 5V regulated power input/output | 5V | 5V regulated power input |
19 | DIO_15 | GPIO15 or UART2 TXEN ttyTS0 | DIO_15 | CPU DIO |
20 | DIO_16 | GPIO16 or UART2 RXD ttyTS0 | UART2_RXD | UART2 or DIO |
21 | DIO_17 | GPIO17 or UART2 TXD ttyTS0 | UART2_TXD | UART2 or DIO |
22 | DIO_18 | GPIO18 or UART0 TXD ttyAM0 | UART0_TXD | UART0 or DIO |
23 | DIO_19 | GPIO19 or UART0 RXD ttyAM0 | UART0_RXD | UART0 or DIO |
24 | UART1_RXD | UART1 RXD ttyAM1 | UART1_RXD | UART1 or DIO |
25 | UART1_TXD | UART1 TXD ttyAM1 | UART1_TXD | UART1 or DIO |
26 | 1.8V | 1.8V | UART3_RXD | UART3 or DIO |
27 | ADC0 | EP93xx ADC0 | ADC0 | i.MX286 LRADC0 |
28 | ADC1 | EP93xx ADC1 | ADC1 | i.MX286 LRADC1 |
29 | ADC2 | EP93xx ADC2 | ADC2 | i.MX286 LRADC2 |
30 | ADC3 | EP93xx ADC3 | ADC3 | i.MX283 LRADC3 |
31 | GND | Ground | GND | Ground |
32 | ABIT_CLK | EP93xx CPU AC97 | I2S_BIT_CLK | I2S Clock |
33 | ASDO | EP93xx CPU AC97 | I2S_TXD | I2S Data transmit |
34 | ASYNCH | EP93xx CPU AC97 | I2S_FRAME | I2S Frame |
35 | ARST# | EP93xx CPU AC97 | I2S_MCLK | I2S MCLK |
36 | ASDI | EP93xx CPU AC97 | I2S_RXD | I2S Data Receive |
37 | SSP_TX | EP93xx SPI/SSP/I2S signal | SPI_MOSI | SPI Master-out, slave-in |
38 | SSP_RX | EP93xx SPI/SSP/I2S signal | SPI_MISO | SPI Master-in, slave-out |
39 | SSP_FRM | EP93xx SPI/SSP/I2S signal | SPI_CS# | SPI Chip select |
40 | SSP_CLK | EP93xx SPI/SSP/I2S signal | SPI_CLK | SPI Clock |