TS-7400-V2 Migration: Difference between revisions

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Line 16: Line 16:
| TDO
| TDO
| TS Production Reserved
| TS Production Reserved
| I2C Dat
| I2C_DAT
| I2C Data pin
| CPU DIO3_25 or I2C Data
|-
|-
| 2
| 2
Line 39: Line 39:
| 5
| 5
| BLAST_BOOT#
| BLAST_BOOT#
| input, low will hijack CPU SPI bootstrap
| Blast boot (9441 boot)
| FPGA_DIO_0
| FPGA_DIO_0
| DIO (Will change in future hardware rev)
| DIO (Will change in next rev)
|-
|-
| 6
| 6
| TCK
| TCK
| TS Production Reserved
| TS Production Reserved
| I2C Clk
| I2C_CLK
| I2C Clock pin
| DIO3_24 or I2C Clock
|-
|-
| 7
| 7
Line 64: Line 64:
| SPI_MISO
| SPI_MISO
| SPI Master-in, slave-out
| SPI Master-in, slave-out
| SPI_MISO
| SPI_MISO <ref name="spiconn">These two SPI ports are electrically connected and are the same interface</ref>
| SPI Master-in, slave-out
| CPU DIO2_4 or SPI MISO
|-
|-
| 10
| 10
Line 75: Line 75:
| 11
| 11
| BLAST_EE_CS#
| BLAST_EE_CS#
| Chip-select for SPI boot hijack EEPROM
| Chip select 9441 flash
| FPGA_DIO_1
| FPGA_DIO_1
| DIO (Will change in future hardware rev)
| DIO (Will change in next rev)
|-
|-
| 12
| 12
| SPI_MOSI
| SPI_MOSI
| SPI Master-out, slave-in
| SPI Master-out, slave-in
| SPI_MOSI
| SPI_MOSI <ref name="spiconn"></ref>
| SPI Master-out, slave-in
| CPU DIO2_6 or SPI MOSI
|-
|-
| 13
| 13
| FLASH_CS#
| FLASH_CS#
| Chip select for SPI flash on TS-9441  
| Chip select 9441 EEPROM
| FPGA_DIO_2
| FPGA_DIO_2
| DIO (Will change in future hardware rev)
| DIO (Will change in next rev)
|-
|-
| 14
| 14
| SPI_CLK
| SPI_CLK
| SPI clock output
| SPI clock output
| SPI_CLK
| SPI_CLK <ref name="spiconn"></ref>
| SPI clock output
| CPU DIO2_7 or SPI clock
|-
|-
| 15
| 15
Line 105: Line 105:
| 16
| 16
| EXT_RESET#
| EXT_RESET#
| External reset input, low triggers board reset
| External reset input
| HARD_REBOOT#
| HARD_REBOOT#
| External reset input, low triggers board reset
| External reset input
|-
|-
| 17
| 17
Line 113: Line 113:
| Boot hijacker present input
| Boot hijacker present input
| FPGA_DIO_3
| FPGA_DIO_3
| DIO (Will change in future hardware rev)
| DIO (Will change in next rev)
|-
|-
| 18
| 18
Line 125: Line 125:
| CPU DIO
| CPU DIO
| DIO_19
| DIO_19
| CPU DIO
| CPU DIO1_24
|-
|-
| 20
| 20
Line 135: Line 135:
| 21
| 21
| EN_5V
| EN_5V
| Switching power supply enable, open-drain
| Switching power supply en
| FPGA_DIO_4
| FPGA_DIO_4
| DIO (Will change in future hardware rev)
| DIO (Will change in next rev)
|-
|-
| 22
| 22
| EP_USB+
| EP_USB+
| EP93xx CPU USB port data signal
| EP93xx USB data
| USB_OTG_P
| USB_OTG_P
| i.MX286 USB OTG port data signal
| i.MX286 USB OTG data
|-
|-
| 23
| 23
Line 149: Line 149:
| Reserved
| Reserved
| FPGA_DIO_5
| FPGA_DIO_5
| DIO (Will change in future hardware rev)
| DIO (Will change in next rev)
|-
|-
| 24
| 24
| EP_USB-
| EP_USB-
| EP93xx CPU USB port data signal
| EP93xx USB data
| USB_OTG_M
| USB_OTG_M
| i.MX286 USB OTG port data signal
| i.MX286 USB OTG data
|-
|-
| 25
| 25
Line 161: Line 161:
| CPU connected GPIO pin
| CPU connected GPIO pin
| DIO_25
| DIO_25
| CPU DIO
| CPU DIO1_25
|-
|-
| 26
| 26
Line 186: Line 186:
| GPIO0 or GPBUS AD0
| GPIO0 or GPBUS AD0
| DIO_00
| DIO_00
| CPU DIO
| CPU DIO1_16
|-
|-
| 2
| 2
Line 198: Line 198:
| GPIO1 or GPBUS AD1
| GPIO1 or GPBUS AD1
| DIO_01
| DIO_01
| CPU DIO
| CPU DIO1_17
|-
|-
| 4
| 4
Line 204: Line 204:
| GPIO2 or GPBUS AD2
| GPIO2 or GPBUS AD2
| DIO_02
| DIO_02
| CPU DIO
| CPU DIO1_18
|-
|-
| 5
| 5
Line 210: Line 210:
| GPIO3 or GPBUS AD3
| GPIO3 or GPBUS AD3
| DIO_03
| DIO_03
| CPU DIO
| CPU DIO1_19
|-
|-
| 6
| 6
Line 216: Line 216:
| GPIO4 or GPBUS AD4
| GPIO4 or GPBUS AD4
| DIO_04
| DIO_04
| CPU DIO
| CPU DIO1_20
|-
|-
| 7
| 7
Line 222: Line 222:
| GPIO5 or GPBUS AD5
| GPIO5 or GPBUS AD5
| DIO_05
| DIO_05
| CPU DIO
| CPU DIO1_21
|-
|-
| 8
| 8
Line 228: Line 228:
| GPIO6 or GPBUS AD6
| GPIO6 or GPBUS AD6
| DIO_06
| DIO_06
| CPU DIO
| CPU DIO1_22
|-
|-
| 9  
| 9  
Line 234: Line 234:
| GPIO7 or GPBUS AD7
| GPIO7 or GPBUS AD7
| DIO_07
| DIO_07
| CPU DIO
| CPU DIO1_23
|-
|-
| 10
| 10
Line 240: Line 240:
| GPIO8 or GPBUS ALE
| GPIO8 or GPBUS ALE
| DIO_08
| DIO_08
| CPU DIO
| CPU DIO1_15
|-
|-
| 11
| 11
Line 246: Line 246:
| GPIO9 or GPBUS RD
| GPIO9 or GPBUS RD
| DIO_09
| DIO_09
| CPU DIO
| CPU DIO1_14
|-
|-
| 12
| 12
Line 258: Line 258:
| GPIO10 or GPBUS WR
| GPIO10 or GPBUS WR
| CAN_RX0
| CAN_RX0
| CAN RX0 or DIO
| CPU DIO3_13 or CAN RX0
|-
|-
| 14
| 14
Line 264: Line 264:
| GPIO11 or GPBUS IRQ
| GPIO11 or GPBUS IRQ
| CAN_RX1
| CAN_RX1
| CAN RX1 or DIO
| CPU DIO3_15 or CAN RX1
|-
|-
| 15
| 15
Line 270: Line 270:
| GPIO12 or GPBUS DRQ
| GPIO12 or GPBUS DRQ
| CAN_TX0
| CAN_TX0
| CAN TX0 or DIO
| CPU DIO3_12 or CAN TX0
|-
|-
| 16
| 16
| DIO_13
| DIO_13
| GPIO13 or GPBUS 14.7456Mhz clock
| GPIO13 or GPBUS 14.7456Mhz
| CAN_TX1
| CAN_TX1
| CAN TX1 or DIO
| CPU DIO3_14 or CAN TX1
|-
|-
| 17
| 17
Line 282: Line 282:
| GPIO14
| GPIO14
| UART3_TXD
| UART3_TXD
| UART3 or DIO
| CPU DIO2_19 or UART3 ttySP3
|-
|-
| 18
| 18
Line 294: Line 294:
| GPIO15 or UART2 TXEN ttyTS0
| GPIO15 or UART2 TXEN ttyTS0
| DIO_15
| DIO_15
| CPU DIO
| CPU DIO3_29 or PWM4
|-
|-
| 20
| 20
Line 300: Line 300:
| GPIO16 or UART2 RXD ttyTS0
| GPIO16 or UART2 RXD ttyTS0
| UART2_RXD
| UART2_RXD
| UART2 or DIO
| CPU DIO2_16 or UART2 ttySP2
|-
|-
| 21
| 21
Line 306: Line 306:
| GPIO17 or UART2 TXD ttyTS0
| GPIO17 or UART2 TXD ttyTS0
| UART2_TXD
| UART2_TXD
| UART2 or DIO
| CPU DIO2_17 or UART2 ttySP2
|-
|-
| 22
| 22
Line 312: Line 312:
| GPIO18 or UART0 TXD ttyAM0
| GPIO18 or UART0 TXD ttyAM0
| UART0_TXD  
| UART0_TXD  
| UART0 or DIO
| CPU DIO3_01 or UART0 ttySP0
|-
|-
| 23
| 23
Line 318: Line 318:
| GPIO19 or UART0 RXD ttyAM0
| GPIO19 or UART0 RXD ttyAM0
| UART0_RXD
| UART0_RXD
| UART0 or DIO
| CPU DIO3_00 or UART0 ttySP0
|-
|-
| 24
| 24
Line 324: Line 324:
| UART1 RXD ttyAM1
| UART1 RXD ttyAM1
| UART1_RXD
| UART1_RXD
| UART1 or DIO
| CPU DIO3_04 or UART1 ttySP1
|-
|-
| 25
| 25
Line 330: Line 330:
| UART1 TXD ttyAM1
| UART1 TXD ttyAM1
| UART1_TXD
| UART1_TXD
| UART1 or DIO
| CPU DIO3_05 or UART1 ttySP1
|-
|-
| 26
| 26
Line 336: Line 336:
| 1.8V
| 1.8V
| UART3_RXD
| UART3_RXD
| UART3 or DIO
| CPU DIO2_18 or UART3 ttySP3
|-
|-
| 27
| 27
Line 372: Line 372:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_BIT_CLK
| I2S_BIT_CLK
| I2S Clock
| CPU DIO3_22 or I2S Clock
|-
|-
| 33
| 33
Line 378: Line 378:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_TXD
| I2S_TXD
| I2S Data transmit
| CPU DIO3_23 or I2S TXD
|-
|-
| 34
| 34
Line 384: Line 384:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_FRAME
| I2S_FRAME
| I2S Frame
| CPU DIO3_21 or I2S Frame
|-
|-
| 35
| 35
Line 390: Line 390:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_MCLK
| I2S_MCLK
| I2S MCLK
| CPU DIO3_20 or I2S MCLK
|-
|-
| 36
| 36
Line 396: Line 396:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_RXD
| I2S_RXD
| I2S Data Receive
| CPU DIO3_26 or I2S RXD
|-
|-
| 37
| 37
| SSP_TX
| SSP_TX
| EP93xx SPI/SSP/I2S signal
| EP93xx SPI/SSP/I2S signal
| SPI_MOSI
| SPI_MOSI <ref name="spiconn"></ref>
| SPI Master-out, slave-in
| CPU DIO2_6 or SPI MOSI
|-
|-
| 38
| 38
| SSP_RX
| SSP_RX
| EP93xx SPI/SSP/I2S signal
| EP93xx SPI/SSP/I2S signal
| SPI_MISO
| SPI_MISO <ref name="spiconn"></ref>
| SPI Master-in, slave-out
| CPU DIO2_4 or SPI MISO
|-
|-
| 39
| 39
| SSP_FRM
| SSP_FRM
| EP93xx SPI/SSP/I2S signal
| EP93xx SPI/SSP/I2S signal
| SPI_CS#
| SPI_CS# <ref name="spiconn"></ref>
| SPI Chip select
| CPU DIO2_05 or SPI Chip select
|-
|-
| 40
| 40
| SSP_CLK
| SSP_CLK
| EP93xx SPI/SSP/I2S signal
| EP93xx SPI/SSP/I2S signal
| SPI_CLK
| SPI_CLK <ref name="spiconn"></ref>
| SPI Clock
| CPU DIO2_7 or SPI clock
|}
|}
<references/>

Revision as of 16:45, 17 September 2013

Pin-by-pin comparison

Upper header pin-out (26-pin)

TS-7400 TS-7400_V2
Pin # Name Function Name Function
1 TDO TS Production Reserved I2C_DAT CPU DIO3_25 or I2C Data
2 TMS TS Production Reserved SD_BOOT# Boot mode pin (SD or NAND)
3 GND Ground GND Ground
4 TDI TS Production Reserved GND Ground
5 BLAST_BOOT# Blast boot (9441 boot) FPGA_DIO_0 DIO (Will change in next rev)
6 TCK TS Production Reserved I2C_CLK DIO3_24 or I2C Clock
7 UART0_TXD UART0 TXD ttyAM0 DEBUG_TXD Debug UART TXD ttyAM0
8 UART0_RXD UART0 RXD ttyAM0 DEBUG_RXD Debug UART RX ttyAM0
9 SPI_MISO SPI Master-in, slave-out SPI_MISO [1] CPU DIO2_4 or SPI MISO
10 3.3V 3.3V Output 3.3V 3.3V Output
11 BLAST_EE_CS# Chip select 9441 flash FPGA_DIO_1 DIO (Will change in next rev)
12 SPI_MOSI SPI Master-out, slave-in SPI_MOSI [1] CPU DIO2_6 or SPI MOSI
13 FLASH_CS# Chip select 9441 EEPROM FPGA_DIO_2 DIO (Will change in next rev)
14 SPI_CLK SPI clock output SPI_CLK [1] CPU DIO2_7 or SPI clock
15 5V 5V regulated power input 5V 5V regulated power input
16 EXT_RESET# External reset input HARD_REBOOT# External reset input
17 BLAST_PRESENT# Boot hijacker present input FPGA_DIO_3 DIO (Will change in next rev)
18 GND Ground GND Ground
19 PORTB_4 CPU DIO DIO_19 CPU DIO1_24
20 GND Ground GND Ground
21 EN_5V Switching power supply en FPGA_DIO_4 DIO (Will change in next rev)
22 EP_USB+ EP93xx USB data USB_OTG_P i.MX286 USB OTG data
23 FIL_VIN Reserved FPGA_DIO_5 DIO (Will change in next rev)
24 EP_USB- EP93xx USB data USB_OTG_M i.MX286 USB OTG data
25 PORTB_7 CPU connected GPIO pin DIO_25 CPU DIO1_25
26 USB_5V USB 5V power USB_SW_5V Switched USB 5V power

Lower header pin-put (40-pin)

TS-7400 TS-7400_V2
Pin # Name Function Name Function
1 DIO_00 GPIO0 or GPBUS AD0 DIO_00 CPU DIO1_16
2 3.3V 3.3V Output 3.3V 3.3V Output
3 DIO_01 GPIO1 or GPBUS AD1 DIO_01 CPU DIO1_17
4 DIO_02 GPIO2 or GPBUS AD2 DIO_02 CPU DIO1_18
5 DIO_03 GPIO3 or GPBUS AD3 DIO_03 CPU DIO1_19
6 DIO_04 GPIO4 or GPBUS AD4 DIO_04 CPU DIO1_20
7 DIO_05 GPIO5 or GPBUS AD5 DIO_05 CPU DIO1_21
8 DIO_06 GPIO6 or GPBUS AD6 DIO_06 CPU DIO1_22
9 DIO_07 GPIO7 or GPBUS AD7 DIO_07 CPU DIO1_23
10 DIO_08 GPIO8 or GPBUS ALE DIO_08 CPU DIO1_15
11 DIO_09 GPIO9 or GPBUS RD DIO_09 CPU DIO1_14
12 GND Ground GND Ground
13 DIO_10 GPIO10 or GPBUS WR CAN_RX0 CPU DIO3_13 or CAN RX0
14 DIO_11 GPIO11 or GPBUS IRQ CAN_RX1 CPU DIO3_15 or CAN RX1
15 DIO_15 GPIO12 or GPBUS DRQ CAN_TX0 CPU DIO3_12 or CAN TX0
16 DIO_13 GPIO13 or GPBUS 14.7456Mhz CAN_TX1 CPU DIO3_14 or CAN TX1
17 DIO_14 GPIO14 UART3_TXD CPU DIO2_19 or UART3 ttySP3
18 5V 5V regulated power input/output 5V 5V regulated power input
19 DIO_15 GPIO15 or UART2 TXEN ttyTS0 DIO_15 CPU DIO3_29 or PWM4
20 DIO_16 GPIO16 or UART2 RXD ttyTS0 UART2_RXD CPU DIO2_16 or UART2 ttySP2
21 DIO_17 GPIO17 or UART2 TXD ttyTS0 UART2_TXD CPU DIO2_17 or UART2 ttySP2
22 DIO_18 GPIO18 or UART0 TXD ttyAM0 UART0_TXD CPU DIO3_01 or UART0 ttySP0
23 DIO_19 GPIO19 or UART0 RXD ttyAM0 UART0_RXD CPU DIO3_00 or UART0 ttySP0
24 UART1_RXD UART1 RXD ttyAM1 UART1_RXD CPU DIO3_04 or UART1 ttySP1
25 UART1_TXD UART1 TXD ttyAM1 UART1_TXD CPU DIO3_05 or UART1 ttySP1
26 1.8V 1.8V UART3_RXD CPU DIO2_18 or UART3 ttySP3
27 ADC0 EP93xx ADC0 ADC0 i.MX286 LRADC0
28 ADC1 EP93xx ADC1 ADC1 i.MX286 LRADC1
29 ADC2 EP93xx ADC2 ADC2 i.MX286 LRADC2
30 ADC3 EP93xx ADC3 ADC3 i.MX283 LRADC3
31 GND Ground GND Ground
32 ABIT_CLK EP93xx CPU AC97 I2S_BIT_CLK CPU DIO3_22 or I2S Clock
33 ASDO EP93xx CPU AC97 I2S_TXD CPU DIO3_23 or I2S TXD
34 ASYNCH EP93xx CPU AC97 I2S_FRAME CPU DIO3_21 or I2S Frame
35 ARST# EP93xx CPU AC97 I2S_MCLK CPU DIO3_20 or I2S MCLK
36 ASDI EP93xx CPU AC97 I2S_RXD CPU DIO3_26 or I2S RXD
37 SSP_TX EP93xx SPI/SSP/I2S signal SPI_MOSI [1] CPU DIO2_6 or SPI MOSI
38 SSP_RX EP93xx SPI/SSP/I2S signal SPI_MISO [1] CPU DIO2_4 or SPI MISO
39 SSP_FRM EP93xx SPI/SSP/I2S signal SPI_CS# [1] CPU DIO2_05 or SPI Chip select
40 SSP_CLK EP93xx SPI/SSP/I2S signal SPI_CLK [1] CPU DIO2_7 or SPI clock
  1. ↑ 1.0 1.1 1.2 1.3 1.4 1.5 1.6 These two SPI ports are electrically connected and are the same interface
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