TS-7400-V2 Migration: Difference between revisions

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(added DIO section)
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=Migration=
The i.MX286 based TS-7400_V2 is designed as a direct upgrade path from the EP9302 based TS-7400.  While these SBCs have the same form factor and a very identical pinout, there are a few software concerns that need to be addressed.  Since the TS-7400_V2 utilizes a different CPU than the TS-7400, accessing any of the DIO or peripherals directly though memory mapped addresses will require code differences between the two SBCs.  Pinouts are matched as best as possible between the two SBCs, however some pins may not apply from one to the other.  This makes for a minor amount of hardware differences which may affect your upgrade.  This guide is intended to provide details in differences between the TS-7400 and TS-7400_V2, for both hardware and software.  This guide will also link to relevant sections of the TS-7400_V2 manual for more in-depth information on software and hardware ports.
=Pin-by-pin comparison=
=Pin-by-pin comparison=


Line 17: Line 20:
| TS Production Reserved
| TS Production Reserved
| I2C_DAT
| I2C_DAT
| CPU DIO3_25 or I2C Data
| [[#DIO|CPU DIO3_25]] or I2C Data
|-
|-
| 2
| 2
Line 47: Line 50:
| TS Production Reserved
| TS Production Reserved
| I2C_CLK
| I2C_CLK
| DIO3_24 or I2C Clock
| [[#DIO|CPU DIO3_24]] or I2C Clock
|-
|-
| 7
| 7
Line 65: Line 68:
| SPI Master-in, slave-out
| SPI Master-in, slave-out
| SPI_MISO <ref name="spiconn">These two SPI ports are electrically connected and are the same interface</ref>
| SPI_MISO <ref name="spiconn">These two SPI ports are electrically connected and are the same interface</ref>
| CPU DIO2_4 or SPI MISO
| [[#DIO|CPU DIO2_04]] or SPI MISO
|-
|-
| 10
| 10
Line 83: Line 86:
| SPI Master-out, slave-in
| SPI Master-out, slave-in
| SPI_MOSI <ref name="spiconn"></ref>
| SPI_MOSI <ref name="spiconn"></ref>
| CPU DIO2_6 or SPI MOSI
| [[#DIO|CPU DIO2_06]] or SPI MOSI
|-
|-
| 13
| 13
Line 95: Line 98:
| SPI clock output
| SPI clock output
| SPI_CLK <ref name="spiconn"></ref>
| SPI_CLK <ref name="spiconn"></ref>
| CPU DIO2_7 or SPI clock
| [[#DIO|CPU DIO2_07]] or SPI clock
|-
|-
| 15
| 15
Line 125: Line 128:
| CPU DIO
| CPU DIO
| DIO_19
| DIO_19
| CPU DIO1_24
| [[#DIO|CPU DIO1_24]]
|-
|-
| 20
| 20
Line 136: Line 139:
| EN_5V
| EN_5V
| Switching power supply en
| Switching power supply en
| FPGA_DIO_4
| FPGA_DIO_04
| DIO (Will change in next rev)
| DIO (Will change in next rev)
|-
|-
Line 161: Line 164:
| CPU connected GPIO pin
| CPU connected GPIO pin
| DIO_25
| DIO_25
| CPU DIO1_25
| [[#DIO|CPU DIO1_25]]
|-
|-
| 26
| 26
Line 186: Line 189:
| GPIO0 or GPBUS AD0
| GPIO0 or GPBUS AD0
| DIO_00
| DIO_00
| CPU DIO1_16
| [[#DIO|CPU DIO1_16]]
|-
|-
| 2
| 2
Line 198: Line 201:
| GPIO1 or GPBUS AD1
| GPIO1 or GPBUS AD1
| DIO_01
| DIO_01
| CPU DIO1_17
| [[#DIO|CPU DIO1_17]]
|-
|-
| 4
| 4
Line 204: Line 207:
| GPIO2 or GPBUS AD2
| GPIO2 or GPBUS AD2
| DIO_02
| DIO_02
| CPU DIO1_18
| [[#DIO|CPU DIO1_18]]
|-
|-
| 5
| 5
Line 210: Line 213:
| GPIO3 or GPBUS AD3
| GPIO3 or GPBUS AD3
| DIO_03
| DIO_03
| CPU DIO1_19
| [[#DIO|CPU DIO1_19]]
|-
|-
| 6
| 6
Line 216: Line 219:
| GPIO4 or GPBUS AD4
| GPIO4 or GPBUS AD4
| DIO_04
| DIO_04
| CPU DIO1_20
| [[#DIO|CPU DIO1_20]]
|-
|-
| 7
| 7
Line 222: Line 225:
| GPIO5 or GPBUS AD5
| GPIO5 or GPBUS AD5
| DIO_05
| DIO_05
| CPU DIO1_21
| [[#DIO|CPU DIO1_21]]
|-
|-
| 8
| 8
Line 228: Line 231:
| GPIO6 or GPBUS AD6
| GPIO6 or GPBUS AD6
| DIO_06
| DIO_06
| CPU DIO1_22
| [[#DIO|CPU DIO1_22]]
|-
|-
| 9  
| 9  
Line 234: Line 237:
| GPIO7 or GPBUS AD7
| GPIO7 or GPBUS AD7
| DIO_07
| DIO_07
| CPU DIO1_23
| [[#DIO|CPU DIO1_23]]
|-
|-
| 10
| 10
Line 240: Line 243:
| GPIO8 or GPBUS ALE
| GPIO8 or GPBUS ALE
| DIO_08
| DIO_08
| CPU DIO1_15
| [[#DIO|CPU DIO1_15]]
|-
|-
| 11
| 11
Line 246: Line 249:
| GPIO9 or GPBUS RD
| GPIO9 or GPBUS RD
| DIO_09
| DIO_09
| CPU DIO1_14
| [[#DIO|CPU DIO1_14]]
|-
|-
| 12
| 12
Line 258: Line 261:
| GPIO10 or GPBUS WR
| GPIO10 or GPBUS WR
| CAN_RX0
| CAN_RX0
| CPU DIO3_13 or CAN RX0
| [[#DIO|CPU DIO3_13]] or CAN RX0
|-
|-
| 14
| 14
Line 264: Line 267:
| GPIO11 or GPBUS IRQ
| GPIO11 or GPBUS IRQ
| CAN_RX1
| CAN_RX1
| CPU DIO3_15 or CAN RX1
| [[#DIO|CPU DIO3_15]] or CAN RX1
|-
|-
| 15
| 15
Line 270: Line 273:
| GPIO12 or GPBUS DRQ
| GPIO12 or GPBUS DRQ
| CAN_TX0
| CAN_TX0
| CPU DIO3_12 or CAN TX0
| [[#DIO|CPU DIO3_12]] or CAN TX0
|-
|-
| 16
| 16
Line 276: Line 279:
| GPIO13 or GPBUS 14.7456Mhz
| GPIO13 or GPBUS 14.7456Mhz
| CAN_TX1
| CAN_TX1
| CPU DIO3_14 or CAN TX1
| [[#DIO|CPU DIO3_14]] or CAN TX1
|-
|-
| 17
| 17
Line 282: Line 285:
| GPIO14
| GPIO14
| UART3_TXD
| UART3_TXD
| CPU DIO2_19 or UART3 ttySP3
| [[#DIO|CPU DIO2_19]] or UART3 ttySP3
|-
|-
| 18
| 18
Line 294: Line 297:
| GPIO15 or UART2 TXEN ttyTS0
| GPIO15 or UART2 TXEN ttyTS0
| DIO_15
| DIO_15
| CPU DIO3_29 or PWM4
| [[#DIO|CPU DIO3_29]] or PWM4
|-
|-
| 20
| 20
Line 300: Line 303:
| GPIO16 or UART2 RXD ttyTS0
| GPIO16 or UART2 RXD ttyTS0
| UART2_RXD
| UART2_RXD
| CPU DIO2_16 or UART2 ttySP2
| [[#DIO|CPU DIO2_16]] or UART2 ttySP2
|-
|-
| 21
| 21
Line 306: Line 309:
| GPIO17 or UART2 TXD ttyTS0
| GPIO17 or UART2 TXD ttyTS0
| UART2_TXD
| UART2_TXD
| CPU DIO2_17 or UART2 ttySP2
| [[#DIO|CPU DIO2_17]] or UART2 ttySP2
|-
|-
| 22
| 22
Line 312: Line 315:
| GPIO18 or UART0 TXD ttyAM0
| GPIO18 or UART0 TXD ttyAM0
| UART0_TXD  
| UART0_TXD  
| CPU DIO3_01 or UART0 ttySP0
| [[#DIO|CPU DIO3_01]] or UART0 ttySP0
|-
|-
| 23
| 23
Line 318: Line 321:
| GPIO19 or UART0 RXD ttyAM0
| GPIO19 or UART0 RXD ttyAM0
| UART0_RXD
| UART0_RXD
| CPU DIO3_00 or UART0 ttySP0
| [[#DIO|CPU DIO3_00]] or UART0 ttySP0
|-
|-
| 24
| 24
Line 324: Line 327:
| UART1 RXD ttyAM1
| UART1 RXD ttyAM1
| UART1_RXD
| UART1_RXD
| CPU DIO3_04 or UART1 ttySP1
| [[#DIO|CPU DIO3_04]] or UART1 ttySP1
|-
|-
| 25
| 25
Line 330: Line 333:
| UART1 TXD ttyAM1
| UART1 TXD ttyAM1
| UART1_TXD
| UART1_TXD
| CPU DIO3_05 or UART1 ttySP1
| [[#DIO|CPU DIO3_05]] or UART1 ttySP1
|-
|-
| 26
| 26
Line 336: Line 339:
| 1.8V
| 1.8V
| UART3_RXD
| UART3_RXD
| CPU DIO2_18 or UART3 ttySP3
| [[#DIO|CPU DIO2_18]] or UART3 ttySP3
|-
|-
| 27
| 27
Line 372: Line 375:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_BIT_CLK
| I2S_BIT_CLK
| CPU DIO3_22 or I2S Clock
| [[#DIO|CPU DIO3_22]] or I2S Clock
|-
|-
| 33
| 33
Line 378: Line 381:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_TXD
| I2S_TXD
| CPU DIO3_23 or I2S TXD
| [[#DIO|CPU DIO3_23]] or I2S TXD
|-
|-
| 34
| 34
Line 384: Line 387:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_FRAME
| I2S_FRAME
| CPU DIO3_21 or I2S Frame
| [[#DIO|CPU DIO3_21]] or I2S Frame
|-
|-
| 35
| 35
Line 390: Line 393:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_MCLK
| I2S_MCLK
| CPU DIO3_20 or I2S MCLK
| [[#DIO|CPU DIO3_20]] or I2S MCLK
|-
|-
| 36
| 36
Line 396: Line 399:
| EP93xx CPU AC97
| EP93xx CPU AC97
| I2S_RXD
| I2S_RXD
| CPU DIO3_26 or I2S RXD
| [[#DIO|CPU DIO3_26]] or I2S RXD
|-
|-
| 37
| 37
Line 402: Line 405:
| EP93xx SPI/SSP/I2S signal
| EP93xx SPI/SSP/I2S signal
| SPI_MOSI <ref name="spiconn"></ref>
| SPI_MOSI <ref name="spiconn"></ref>
| CPU DIO2_6 or SPI MOSI
| [[#DIO|CPU DIO2_06]] or SPI MOSI
|-
|-
| 38
| 38
Line 408: Line 411:
| EP93xx SPI/SSP/I2S signal
| EP93xx SPI/SSP/I2S signal
| SPI_MISO <ref name="spiconn"></ref>
| SPI_MISO <ref name="spiconn"></ref>
| CPU DIO2_4 or SPI MISO
| [[#DIO|CPU DIO2_04]] or SPI MISO
|-
|-
| 39
| 39
Line 414: Line 417:
| EP93xx SPI/SSP/I2S signal
| EP93xx SPI/SSP/I2S signal
| SPI_CS# <ref name="spiconn"></ref>
| SPI_CS# <ref name="spiconn"></ref>
| CPU DIO2_05 or SPI Chip select
| [[#DIO|CPU DIO2_05]] or SPI Chip select
|-
|-
| 40
| 40
Line 420: Line 423:
| EP93xx SPI/SSP/I2S signal
| EP93xx SPI/SSP/I2S signal
| SPI_CLK <ref name="spiconn"></ref>
| SPI_CLK <ref name="spiconn"></ref>
| CPU DIO2_7 or SPI clock
| [[#DIO|CPU DIO2_07]] or SPI clock
|}
|}


<references/>
<references/>
=Peripheral Functions=
==GPBUS==
At this time the GPBUS provided on the TS-7400 has not been ported over to the TS-7400_V2.  This is a very simplistic bus that can easily be implemented in DIO.  Contact Technologic Systems for more information on this
==DIO==
There are a few fundamental differences between DIO access on the TS-7400 and the TS-7400_V2.  On the TS-7400_V2 nearly every pin has multiple functions associated with it, one of them being DIO, and one to three of them being other CPU peripherals.  This mux must be set to DIO mode before a pin can be utilized as a DIO.  The TS-7400 refers to different DIO clusters as "Ports" that are then subdivided in to pins, i.e. PORTA_1, PORTB_7, etc.  The TS-7400_V2 has groupings of all pins held in "Banks" that are subdivided in to pins, i.e. DIO3_20, DIO2_16, etc.  The bank and pin number are important to driving the correct DIO pin.  All DIO and its associated registers are able to be accessed at base 0x80018000 with all resisters residing within a 4kbyte address space. 
Code changes should not require great amounts of additional code to support the changed DIO.  Differences should include mmap()ing the new base address, additional memory accesses to the MUXSEL register(s) to put the needed DIO in the correct mode, using a different address for DOE (Formerly the Data Direction Register in the TS-7400 EP9302), using a different address for DOUT (Formerly the Data Register in the TS-7400 EP9302), and adding calls to the DIN register (Reading DIO states was achieved by reading the Data Register in the TS-7400 EP9302).  Please note that each register actually has 4 addresses associated with it in order to provide atomic set/clear/toggle accesses, a read/write register (Same as standard registers in the TS-7400 EP9302), a set address, a clear address, and a toggle address.  Any bits written as a 1 to the set/clear/toggle address will cause that bit to be set/cleared/toggled atomically in the register.
On the TS-7400_V2 most pins start up in DIO while others are in peripheral.  Those that start up in a peripheral mode will likely have a kernel driver associated with them.  Changing the MUXSEL bits of any pin that is a peripheral may result in system instability, loss of peripheral functionality, or the associated MUXSEL register being set back in to peripheral mode by the driver with no warning.  Please verify that any pin(s) to be used do not have a loaded and running kernel module to support a peripheral used on the aforementioned pin(s).
Each pin is also interrupt capable.  Combined with our userspace IRQs, it allows interrupt driven userspace applications to be written very easily.
See the TS-7400_V2 manual and the i.MX28 manual for more information.

Revision as of 18:20, 17 September 2013

Migration

The i.MX286 based TS-7400_V2 is designed as a direct upgrade path from the EP9302 based TS-7400. While these SBCs have the same form factor and a very identical pinout, there are a few software concerns that need to be addressed. Since the TS-7400_V2 utilizes a different CPU than the TS-7400, accessing any of the DIO or peripherals directly though memory mapped addresses will require code differences between the two SBCs. Pinouts are matched as best as possible between the two SBCs, however some pins may not apply from one to the other. This makes for a minor amount of hardware differences which may affect your upgrade. This guide is intended to provide details in differences between the TS-7400 and TS-7400_V2, for both hardware and software. This guide will also link to relevant sections of the TS-7400_V2 manual for more in-depth information on software and hardware ports.

Pin-by-pin comparison

Upper header pin-out (26-pin)

TS-7400 TS-7400_V2
Pin # Name Function Name Function
1 TDO TS Production Reserved I2C_DAT CPU DIO3_25 or I2C Data
2 TMS TS Production Reserved SD_BOOT# Boot mode pin (SD or NAND)
3 GND Ground GND Ground
4 TDI TS Production Reserved GND Ground
5 BLAST_BOOT# Blast boot (9441 boot) FPGA_DIO_0 DIO (Will change in next rev)
6 TCK TS Production Reserved I2C_CLK CPU DIO3_24 or I2C Clock
7 UART0_TXD UART0 TXD ttyAM0 DEBUG_TXD Debug UART TXD ttyAM0
8 UART0_RXD UART0 RXD ttyAM0 DEBUG_RXD Debug UART RX ttyAM0
9 SPI_MISO SPI Master-in, slave-out SPI_MISO [1] CPU DIO2_04 or SPI MISO
10 3.3V 3.3V Output 3.3V 3.3V Output
11 BLAST_EE_CS# Chip select 9441 flash FPGA_DIO_1 DIO (Will change in next rev)
12 SPI_MOSI SPI Master-out, slave-in SPI_MOSI [1] CPU DIO2_06 or SPI MOSI
13 FLASH_CS# Chip select 9441 EEPROM FPGA_DIO_2 DIO (Will change in next rev)
14 SPI_CLK SPI clock output SPI_CLK [1] CPU DIO2_07 or SPI clock
15 5V 5V regulated power input 5V 5V regulated power input
16 EXT_RESET# External reset input HARD_REBOOT# External reset input
17 BLAST_PRESENT# Boot hijacker present input FPGA_DIO_3 DIO (Will change in next rev)
18 GND Ground GND Ground
19 PORTB_4 CPU DIO DIO_19 CPU DIO1_24
20 GND Ground GND Ground
21 EN_5V Switching power supply en FPGA_DIO_04 DIO (Will change in next rev)
22 EP_USB+ EP93xx USB data USB_OTG_P i.MX286 USB OTG data
23 FIL_VIN Reserved FPGA_DIO_5 DIO (Will change in next rev)
24 EP_USB- EP93xx USB data USB_OTG_M i.MX286 USB OTG data
25 PORTB_7 CPU connected GPIO pin DIO_25 CPU DIO1_25
26 USB_5V USB 5V power USB_SW_5V Switched USB 5V power

Lower header pin-put (40-pin)

TS-7400 TS-7400_V2
Pin # Name Function Name Function
1 DIO_00 GPIO0 or GPBUS AD0 DIO_00 CPU DIO1_16
2 3.3V 3.3V Output 3.3V 3.3V Output
3 DIO_01 GPIO1 or GPBUS AD1 DIO_01 CPU DIO1_17
4 DIO_02 GPIO2 or GPBUS AD2 DIO_02 CPU DIO1_18
5 DIO_03 GPIO3 or GPBUS AD3 DIO_03 CPU DIO1_19
6 DIO_04 GPIO4 or GPBUS AD4 DIO_04 CPU DIO1_20
7 DIO_05 GPIO5 or GPBUS AD5 DIO_05 CPU DIO1_21
8 DIO_06 GPIO6 or GPBUS AD6 DIO_06 CPU DIO1_22
9 DIO_07 GPIO7 or GPBUS AD7 DIO_07 CPU DIO1_23
10 DIO_08 GPIO8 or GPBUS ALE DIO_08 CPU DIO1_15
11 DIO_09 GPIO9 or GPBUS RD DIO_09 CPU DIO1_14
12 GND Ground GND Ground
13 DIO_10 GPIO10 or GPBUS WR CAN_RX0 CPU DIO3_13 or CAN RX0
14 DIO_11 GPIO11 or GPBUS IRQ CAN_RX1 CPU DIO3_15 or CAN RX1
15 DIO_15 GPIO12 or GPBUS DRQ CAN_TX0 CPU DIO3_12 or CAN TX0
16 DIO_13 GPIO13 or GPBUS 14.7456Mhz CAN_TX1 CPU DIO3_14 or CAN TX1
17 DIO_14 GPIO14 UART3_TXD CPU DIO2_19 or UART3 ttySP3
18 5V 5V regulated power input/output 5V 5V regulated power input
19 DIO_15 GPIO15 or UART2 TXEN ttyTS0 DIO_15 CPU DIO3_29 or PWM4
20 DIO_16 GPIO16 or UART2 RXD ttyTS0 UART2_RXD CPU DIO2_16 or UART2 ttySP2
21 DIO_17 GPIO17 or UART2 TXD ttyTS0 UART2_TXD CPU DIO2_17 or UART2 ttySP2
22 DIO_18 GPIO18 or UART0 TXD ttyAM0 UART0_TXD CPU DIO3_01 or UART0 ttySP0
23 DIO_19 GPIO19 or UART0 RXD ttyAM0 UART0_RXD CPU DIO3_00 or UART0 ttySP0
24 UART1_RXD UART1 RXD ttyAM1 UART1_RXD CPU DIO3_04 or UART1 ttySP1
25 UART1_TXD UART1 TXD ttyAM1 UART1_TXD CPU DIO3_05 or UART1 ttySP1
26 1.8V 1.8V UART3_RXD CPU DIO2_18 or UART3 ttySP3
27 ADC0 EP93xx ADC0 ADC0 i.MX286 LRADC0
28 ADC1 EP93xx ADC1 ADC1 i.MX286 LRADC1
29 ADC2 EP93xx ADC2 ADC2 i.MX286 LRADC2
30 ADC3 EP93xx ADC3 ADC3 i.MX283 LRADC3
31 GND Ground GND Ground
32 ABIT_CLK EP93xx CPU AC97 I2S_BIT_CLK CPU DIO3_22 or I2S Clock
33 ASDO EP93xx CPU AC97 I2S_TXD CPU DIO3_23 or I2S TXD
34 ASYNCH EP93xx CPU AC97 I2S_FRAME CPU DIO3_21 or I2S Frame
35 ARST# EP93xx CPU AC97 I2S_MCLK CPU DIO3_20 or I2S MCLK
36 ASDI EP93xx CPU AC97 I2S_RXD CPU DIO3_26 or I2S RXD
37 SSP_TX EP93xx SPI/SSP/I2S signal SPI_MOSI [1] CPU DIO2_06 or SPI MOSI
38 SSP_RX EP93xx SPI/SSP/I2S signal SPI_MISO [1] CPU DIO2_04 or SPI MISO
39 SSP_FRM EP93xx SPI/SSP/I2S signal SPI_CS# [1] CPU DIO2_05 or SPI Chip select
40 SSP_CLK EP93xx SPI/SSP/I2S signal SPI_CLK [1] CPU DIO2_07 or SPI clock
  1. ↑ 1.0 1.1 1.2 1.3 1.4 1.5 1.6 These two SPI ports are electrically connected and are the same interface

Peripheral Functions

GPBUS

At this time the GPBUS provided on the TS-7400 has not been ported over to the TS-7400_V2. This is a very simplistic bus that can easily be implemented in DIO. Contact Technologic Systems for more information on this

DIO

There are a few fundamental differences between DIO access on the TS-7400 and the TS-7400_V2. On the TS-7400_V2 nearly every pin has multiple functions associated with it, one of them being DIO, and one to three of them being other CPU peripherals. This mux must be set to DIO mode before a pin can be utilized as a DIO. The TS-7400 refers to different DIO clusters as "Ports" that are then subdivided in to pins, i.e. PORTA_1, PORTB_7, etc. The TS-7400_V2 has groupings of all pins held in "Banks" that are subdivided in to pins, i.e. DIO3_20, DIO2_16, etc. The bank and pin number are important to driving the correct DIO pin. All DIO and its associated registers are able to be accessed at base 0x80018000 with all resisters residing within a 4kbyte address space.

Code changes should not require great amounts of additional code to support the changed DIO. Differences should include mmap()ing the new base address, additional memory accesses to the MUXSEL register(s) to put the needed DIO in the correct mode, using a different address for DOE (Formerly the Data Direction Register in the TS-7400 EP9302), using a different address for DOUT (Formerly the Data Register in the TS-7400 EP9302), and adding calls to the DIN register (Reading DIO states was achieved by reading the Data Register in the TS-7400 EP9302). Please note that each register actually has 4 addresses associated with it in order to provide atomic set/clear/toggle accesses, a read/write register (Same as standard registers in the TS-7400 EP9302), a set address, a clear address, and a toggle address. Any bits written as a 1 to the set/clear/toggle address will cause that bit to be set/cleared/toggled atomically in the register.

On the TS-7400_V2 most pins start up in DIO while others are in peripheral. Those that start up in a peripheral mode will likely have a kernel driver associated with them. Changing the MUXSEL bits of any pin that is a peripheral may result in system instability, loss of peripheral functionality, or the associated MUXSEL register being set back in to peripheral mode by the driver with no warning. Please verify that any pin(s) to be used do not have a loaded and running kernel module to support a peripheral used on the aforementioned pin(s).

Each pin is also interrupt capable. Combined with our userspace IRQs, it allows interrupt driven userspace applications to be written very easily.

See the TS-7400_V2 manual and the i.MX28 manual for more information.

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