TS-7400-V2 Migration

Migration

The i.MX286 based TS-7400_V2 is designed as a direct upgrade path from the EP9302 based TS-7400. While these SBCs have the same form factor and a very identical pinout, there are a few software concerns that need to be addressed. Since the TS-7400_V2 utilizes a different CPU than the TS-7400, accessing any of the DIO or peripherals directly though memory mapped addresses will require code differences between the two SBCs. Pinouts are matched as best as possible between the two SBCs, however some pins may not apply from one to the other. This makes for a minor amount of hardware differences which may affect your upgrade. This guide is intended to provide details in differences between the TS-7400 and TS-7400_V2, for both hardware and software. This guide will also link to relevant sections of the TS-7400_V2 manual for more in-depth information on software and hardware ports.

Pin-by-pin comparison

Upper header pin-out (26-pin)

	TS-7400		TS-7400_V2
Pin #	Name	Function	Name	Function
1	TDO	TS Production Reserved	I2C_DAT	CPU DIO3_25 or I2C Data
2	TMS	TS Production Reserved	SD_BOOT#	Boot mode pin (SD or NAND)
3	GND	Ground	GND	Ground
4	TDI	TS Production Reserved	GND	Ground
5	BLAST_BOOT#	Blast boot (9441 boot)	FPGA_DIO_0	DIO (Will change in next rev)
6	TCK	TS Production Reserved	I2C_CLK	CPU DIO3_24 or I2C Clock
7	UART0_TXD	UART0 TXD	DEBUG_TXD	Debug UART TXD
8	UART0_RXD	UART0 RXD	DEBUG_RXD	Debug UART RX
9	SPI_MISO	SPI Master-in, slave-out	SPI_MISO	CPU DIO2_04 or SPI MISO
10	3.3V	3.3V Output	3.3V	3.3V Output
11	BLAST_EE_CS#	Chip select 9441 flash	FPGA_DIO_1	DIO (Will change in next rev)
12	SPI_MOSI	SPI Master-out, slave-in	SPI_MOSI	CPU DIO2_06 or SPI MOSI
13	FLASH_CS#	Chip select 9441 EEPROM	FPGA_DIO_2	DIO (Will change in next rev)
14	SPI_CLK	SPI clock output	SPI_CLK	CPU DIO2_07 or SPI clock
15	5V	5V regulated power input	5V	5V regulated power input
16	EXT_RESET#	External reset input	HARD_REBOOT#	External reset input
17	BLAST_PRESENT#	Boot hijacker present input	FPGA_DIO_3	DIO (Will change in next rev)
18	GND	Ground	GND	Ground
19	PORTB_4	CPU DIO	DIO_19	CPU DIO1_24
20	GND	Ground	GND	Ground
21	EN_5V	Switching power supply en	FPGA_DIO_04	DIO (Will change in next rev)
22	EP_USB+	EP93xx USB data	USB_OTG_P	i.MX286 USB OTG data
23	FIL_VIN	Reserved	FPGA_DIO_5	DIO (Will change in next rev)
24	EP_USB-	EP93xx USB data	USB_OTG_M	i.MX286 USB OTG data
25	PORTB_7	CPU DIO	DIO_25	CPU DIO1_25
26	USB_5V	USB 5V power	USB_SW_5V	Switched USB 5V power

Lower header pin-put (40-pin)

	TS-7400		TS-7400_V2
Pin #	Name	Function	Name	Function
1	DIO_00	GPIO0 or GPBUS AD0	DIO_00	CPU DIO1_16
2	3.3V	3.3V Output	3.3V	3.3V Output
3	DIO_01	GPIO1 or GPBUS AD1	DIO_01	CPU DIO1_17
4	DIO_02	GPIO2 or GPBUS AD2	DIO_02	CPU DIO1_18
5	DIO_03	GPIO3 or GPBUS AD3	DIO_03	CPU DIO1_19
6	DIO_04	GPIO4 or GPBUS AD4	DIO_04	CPU DIO1_20
7	DIO_05	GPIO5 or GPBUS AD5	DIO_05	CPU DIO1_21
8	DIO_06	GPIO6 or GPBUS AD6	DIO_06	CPU DIO1_22
9	DIO_07	GPIO7 or GPBUS AD7	DIO_07	CPU DIO1_23
10	DIO_08	GPIO8 or GPBUS ALE	DIO_08	CPU DIO1_15
11	DIO_09	GPIO9 or GPBUS RD	DIO_09	CPU DIO1_14
12	GND	Ground	GND	Ground
13	DIO_10	GPIO10 or GPBUS WR	CAN_RX0	CPU DIO3_13 or CAN RX0
14	DIO_11	GPIO11 or GPBUS IRQ	CAN_RX1	CPU DIO3_15 or CAN RX1
15	DIO_15	GPIO12 or GPBUS DRQ	CAN_TX0	CPU DIO3_12 or CAN TX0
16	DIO_13	GPIO13 or GPBUS 14.7456Mhz	CAN_TX1	CPU DIO3_14 or CAN TX1
17	DIO_14	GPIO14	UART3_TXD	CPU DIO2_19 or UART3
18	5V	5V regulated power input/output	5V	5V regulated power input
19	DIO_15	GPIO15 or UART2 TXEN	DIO_15	CPU DIO3_29 or PWM4
20	DIO_16	GPIO16 or UART2 RXD	UART2_RXD	CPU DIO2_16 or UART2
21	DIO_17	GPIO17 or UART2 TXD	UART2_TXD	CPU DIO2_17 or UART2
22	DIO_18	GPIO18 or UART0 TXD	UART0_TXD	CPU DIO3_01 or UART0
23	DIO_19	GPIO19 or UART0 RXD	UART0_RXD	CPU DIO3_00 or UART0
24	UART1_RXD	UART1 RXD	UART1_RXD	CPU DIO3_04 or UART1
25	UART1_TXD	UART1 TXD	UART1_TXD	CPU DIO3_05 or UART1
26	1.8V	1.8V	UART3_RXD	CPU DIO2_18 or UART3
27	ADC0	EP93xx ADC0	ADC0	i.MX286 LRADC0
28	ADC1	EP93xx ADC1	ADC1	i.MX286 LRADC1
29	ADC2	EP93xx ADC2	ADC2	i.MX286 LRADC2
30	ADC3	EP93xx ADC3	ADC3	i.MX283 LRADC3
31	GND	Ground	GND	Ground
32	ABIT_CLK	EP93xx CPU AC97	I2S_BIT_CLK	CPU DIO3_22 or I2S Clock
33	ASDO	EP93xx CPU AC97	I2S_TXD	CPU DIO3_23 or I2S TXD
34	ASYNCH	EP93xx CPU AC97	I2S_FRAME	CPU DIO3_21 or I2S Frame
35	ARST#	EP93xx CPU AC97	I2S_MCLK	CPU DIO3_20 or I2S MCLK
36	ASDI	EP93xx CPU AC97	I2S_RXD	CPU DIO3_26 or I2S RXD
37	SSP_TX	EP93xx SPI/SSP/I2S signal	SPI_MOSI	CPU DIO2_06 or SPI MOSI
38	SSP_RX	EP93xx SPI/SSP/I2S signal	SPI_MISO	CPU DIO2_04 or SPI MISO
39	SSP_FRM	EP93xx SPI/SSP/I2S signal	SPI_CS#	CPU DIO2_05 or SPI Chip select
40	SSP_CLK	EP93xx SPI/SSP/I2S signal	SPI_CLK	CPU DIO2_07 or SPI clock

Peripheral Functions

DIO

There are a few fundamental differences between DIO access on the TS-7400 and the TS-7400_V2. On the TS-7400_V2 nearly every pin has multiple functions associated with it, one of them being DIO, and one to three of them being other CPU peripherals. This mux must be set to DIO mode before a pin can be utilized as a DIO. The TS-7400 refers to different DIO clusters as "Ports" that are then subdivided in to pins, i.e. PORTA_1, PORTB_7, etc. The TS-7400_V2 has groupings of all pins held in "Banks" that are subdivided in to pins, i.e. DIO3_20, DIO2_16, etc. The bank and pin number are important to driving the correct DIO pin. All DIO and its associated registers are able to be accessed at base 0x80018000 with all resisters residing within a 4kbyte address space.

Code changes should not require great amounts of additional code to support the changed DIO. Differences should include mmap()ing the new base address, additional memory accesses to the MUXSEL register(s) to put the needed DIO in the correct mode, using a different address for DOE (Formerly the Data Direction Register in the TS-7400 EP9302), using a different address for DOUT (Formerly the Data Register in the TS-7400 EP9302), and adding calls to the DIN register (Reading DIO states was achieved by reading the Data Register in the TS-7400 EP9302). Please note that each register actually has 4 addresses associated with it in order to provide atomic set/clear/toggle accesses, a read/write register (Same as standard registers in the TS-7400 EP9302), a set address, a clear address, and a toggle address. Any bits written as a 1 to the set/clear/toggle address will cause that bit to be set/cleared/toggled atomically in the register.

On the TS-7400_V2 most pins start up in DIO while others are in peripheral. Those that start up in a peripheral mode will likely have a kernel driver associated with them. Changing the MUXSEL bits of any pin that is a peripheral may result in system instability, loss of peripheral functionality, or the associated MUXSEL register being set back in to peripheral mode by the driver with no warning. Please verify that any pin(s) to be used do not have a loaded and running kernel module to support a peripheral used on the aforementioned pin(s).

Each pin is also interrupt capable. Combined with our userspace IRQs, it allows interrupt driven userspace applications to be written very easily.

See the TS-7400_V2 manual and the i.MX28 manual for more information.

GPBUS

At this time the GPBUS provided on the TS-7400 has not been ported over to the TS-7400_V2. This is a very simplistic bus that can easily be implemented in DIO. Contact Technologic Systems for more information on this

UARTs

The TS-7400_V2 adds more UARTs than the original TS-7400 provids. In linux, the TTY layer takes care of all underlying peripheral and pin access for the various UARTs in the system. Currently all of the UART ports on the TS-7400_V2 start up in peripheral mode, however the kernel drivers are modularized and not loaded by default. These pins are safe to make behave as DIO. In order to change the number of UARTs used by the driver or to make any modifications to the pin muxes or startup states, the kernel will need to be modified. The TS-7400_V2 has a Debug UART that is always intended to be such, in addition to that there are 4 UARTs for a total of 5; the TS-7400 only has 3 UARTs total. Please note that the TS-7400 used UART0 in two places on the pin headers, the TS-7400_V2 replaces one of these with the Debug UART and UART0 is a separate device. All UARTs in the TS-7400_V2 are CPU UARTs. Also note that UART2 does not offer an automatic TXEN on the TS-7400_V2, there is a DIO pin there in its place that can be used as a TXEN.

Code changes should only require changing the device name of the UART(s) used. The setup steps for configuring the port itself will likely require no changes. See the comparison to identify which pins are being used by which UARTs.

Port	TS-7400 name	TS-7400_V2 name
Debug UART		/dev/ttyAM0
UART0	/dev/ttyAM0	/dev/ttySP0
UART1	/dev/ttyAM1	/dev/ttySP1
UART2	/dev/ttyTS0	/dev/ttySP2
UART3		/dev/ttySP3