TS-7400-V2 Migration: Difference between revisions
(Added UART, updated other links in pin table) |
(Added AC97, SPI, I2C) |
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Line 20: | Line 20: | ||
| TS Production Reserved | | TS Production Reserved | ||
| I2C_DAT | | I2C_DAT | ||
| [[#DIO|CPU DIO3_25]] or I2C Data | | [[#DIO|CPU DIO3_25]] or [[#I2C|I2C Data]] | ||
|- | |- | ||
| 2 | | 2 | ||
Line 50: | Line 50: | ||
| TS Production Reserved | | TS Production Reserved | ||
| I2C_CLK | | I2C_CLK | ||
| [[#DIO|CPU DIO3_24]] or I2C Clock | | [[#DIO|CPU DIO3_24]] or [[#I2C|I2C Clock]] | ||
|- | |- | ||
| 7 | | 7 | ||
Line 66: | Line 66: | ||
| 9 | | 9 | ||
| SPI_MISO | | SPI_MISO | ||
| SPI | | [[#SPI|SPI MISO]] | ||
| SPI_MISO <ref name="spiconn">These two SPI ports are electrically connected and are the same interface</ref> | | SPI_MISO <ref name="spiconn">These two SPI ports are electrically connected and are the same interface</ref> | ||
| [[#DIO|CPU DIO2_04]] or SPI MISO | | [[#DIO|CPU DIO2_04]] or [[#SPI|SPI MISO]] | ||
|- | |- | ||
| 10 | | 10 | ||
Line 78: | Line 78: | ||
| 11 | | 11 | ||
| BLAST_EE_CS# | | BLAST_EE_CS# | ||
| Chip select 9441 flash | | [[#SPI|Chip select 9441 flash]] | ||
| FPGA_DIO_1 | | FPGA_DIO_1 | ||
| DIO (Will change in next rev) | | DIO (Will change in next rev) | ||
Line 84: | Line 84: | ||
| 12 | | 12 | ||
| SPI_MOSI | | SPI_MOSI | ||
| SPI | | [[#SPI|SPI MOSI]] | ||
| SPI_MOSI <ref name="spiconn"></ref> | | SPI_MOSI <ref name="spiconn"></ref> | ||
| [[#DIO|CPU DIO2_06]] or SPI MOSI | | [[#DIO|CPU DIO2_06]] or [[#SPI|SPI MOSI]] | ||
|- | |- | ||
| 13 | | 13 | ||
Line 96: | Line 96: | ||
| 14 | | 14 | ||
| SPI_CLK | | SPI_CLK | ||
| SPI clock output | | [[#SPI|SPI clock output]] | ||
| SPI_CLK <ref name="spiconn"></ref> | | SPI_CLK <ref name="spiconn"></ref> | ||
| [[#DIO|CPU DIO2_07]] or SPI clock | | [[#DIO|CPU DIO2_07]] or [[#SPI|SPI clock]] | ||
|- | |- | ||
| 15 | | 15 | ||
Line 187: | Line 187: | ||
| 1 | | 1 | ||
| DIO_00 | | DIO_00 | ||
| [[#DIO|GPIO0]] or GPBUS AD0 | | [[#DIO|GPIO0]] or [[#GPBUS|GPBUS AD0]] | ||
| DIO_00 | | DIO_00 | ||
| [[#DIO|CPU DIO1_16]] | | [[#DIO|CPU DIO1_16]] | ||
Line 294: | Line 294: | ||
|- | |- | ||
| 19 | | 19 | ||
| [[#DIO| | | DIO_15 | ||
| [[#DIO|GPIO15]] or [[#UARTs|UART2 TXEN]] | |||
| DIO_15 | | DIO_15 | ||
| [[#DIO|CPU DIO3_29]] or PWM4 | | [[#DIO|CPU DIO3_29]] or PWM4 | ||
Line 373: | Line 373: | ||
| 32 | | 32 | ||
| ABIT_CLK | | ABIT_CLK | ||
| EP93xx CPU AC97 | | [[#AC'97|EP93xx CPU AC97]] | ||
| I2S_BIT_CLK | | I2S_BIT_CLK | ||
| [[#DIO|CPU DIO3_22]] or I2S Clock | | [[#DIO|CPU DIO3_22]] or I2S Clock | ||
Line 379: | Line 379: | ||
| 33 | | 33 | ||
| ASDO | | ASDO | ||
| EP93xx CPU AC97 | | [[#AC'97|EP93xx CPU AC97]] | ||
| I2S_TXD | | I2S_TXD | ||
| [[#DIO|CPU DIO3_23]] or I2S TXD | | [[#DIO|CPU DIO3_23]] or I2S TXD | ||
Line 385: | Line 385: | ||
| 34 | | 34 | ||
| ASYNCH | | ASYNCH | ||
| EP93xx CPU AC97 | | [[#AC'97|EP93xx CPU AC97]] | ||
| I2S_FRAME | | I2S_FRAME | ||
| [[#DIO|CPU DIO3_21]] or I2S Frame | | [[#DIO|CPU DIO3_21]] or I2S Frame | ||
Line 391: | Line 391: | ||
| 35 | | 35 | ||
| ARST# | | ARST# | ||
| EP93xx CPU AC97 | | [[#AC'97|EP93xx CPU AC97]] | ||
| I2S_MCLK | | I2S_MCLK | ||
| [[#DIO|CPU DIO3_20]] or I2S MCLK | | [[#DIO|CPU DIO3_20]] or I2S MCLK | ||
Line 397: | Line 397: | ||
| 36 | | 36 | ||
| ASDI | | ASDI | ||
| EP93xx CPU AC97 | | [[#AC'97|EP93xx CPU AC97]] | ||
| I2S_RXD | | I2S_RXD | ||
| [[#DIO|CPU DIO3_26]] or I2S RXD | | [[#DIO|CPU DIO3_26]] or I2S RXD | ||
Line 403: | Line 403: | ||
| 37 | | 37 | ||
| SSP_TX | | SSP_TX | ||
| EP93xx SPI/SSP/I2S signal | | EP93xx [[#SPI|SPI/SSP]]/I2S signal | ||
| SPI_MOSI <ref name="spiconn"></ref> | | SPI_MOSI <ref name="spiconn"></ref> | ||
| [[#DIO|CPU DIO2_06]] or SPI MOSI | | [[#DIO|CPU DIO2_06]] or [[#SPI|SPI MOSI]] | ||
|- | |- | ||
| 38 | | 38 | ||
| SSP_RX | | SSP_RX | ||
| EP93xx SPI/SSP/I2S signal | | EP93xx [[#SPI|SPI/SSP]]/I2S signal | ||
| SPI_MISO <ref name="spiconn"></ref> | | SPI_MISO <ref name="spiconn"></ref> | ||
| [[#DIO|CPU DIO2_04]] or SPI MISO | | [[#DIO|CPU DIO2_04]] or [[#SPI|SPI MISO]] | ||
|- | |- | ||
| 39 | | 39 | ||
| SSP_FRM | | SSP_FRM | ||
| EP93xx SPI/SSP/I2S signal | | EP93xx [[#SPI|SPI/SSP]]/I2S signal | ||
| SPI_CS# <ref name="spiconn"></ref> | | SPI_CS# <ref name="spiconn"></ref> | ||
| [[#DIO|CPU DIO2_05]] or SPI Chip select | | [[#DIO|CPU DIO2_05]] or [[#SPI|SPI Chip select]] | ||
|- | |- | ||
| 40 | | 40 | ||
| SSP_CLK | | SSP_CLK | ||
| EP93xx SPI/SSP/I2S signal | | EP93xx [[#SPI|SPI/SSP]]/I2S signal | ||
| SPI_CLK <ref name="spiconn"></ref> | | SPI_CLK <ref name="spiconn"></ref> | ||
| [[#DIO|CPU DIO2_07]] or SPI clock | | [[#DIO|CPU DIO2_07]] or [[#SPI|SPI clock]] | ||
|} | |} | ||
Line 429: | Line 429: | ||
=Peripheral Functions= | =Peripheral Functions= | ||
==AC'97== | |||
The TS-7400_V2 does not offer an AC'97 audio port. Audio functionality can still be achieved by using [[#I2S|I2S]] audio. | |||
==DIO== | ==DIO== | ||
There are a few fundamental differences between DIO access on the TS-7400 and the TS-7400_V2. On the TS-7400_V2 nearly every pin has multiple functions associated with it, one of them being DIO, and one to three of them being other CPU peripherals. This mux must be set to DIO mode before a pin can be utilized as a DIO. The TS-7400 refers to different DIO clusters as "Ports" that are then subdivided in to pins, i.e. PORTA_1, PORTB_7, etc. The TS-7400_V2 has groupings of all pins held in "Banks" that are subdivided in to pins, i.e. DIO3_20, DIO2_16, etc. The bank and pin number are important to driving the correct DIO pin. All DIO and its associated registers are able to be accessed at base 0x80018000 with all resisters residing within a 4kbyte address space. | There are a few fundamental differences between DIO access on the TS-7400 and the TS-7400_V2. On the TS-7400_V2 nearly every pin has multiple functions associated with it, one of them being DIO, and one to three of them being other CPU peripherals. This mux must be set to DIO mode before a pin can be utilized as a DIO. The TS-7400 refers to different DIO clusters as "Ports" that are then subdivided in to pins, i.e. PORTA_1, PORTB_7, etc. The TS-7400_V2 has groupings of all pins held in "Banks" that are subdivided in to pins, i.e. DIO3_20, DIO2_16, etc. The bank and pin number are important to driving the correct DIO pin. All DIO and its associated registers are able to be accessed at base 0x80018000 with all resisters residing within a 4kbyte address space. IRQ settings start at 0x80019000 and are also within a 4kbyte address space, however these registers should not normally need to be modified; any changes to IRQs and their settings should be made in-kernel. | ||
Code changes should not require great amounts of additional code to support the changed DIO. Differences should include mmap()ing the new base address, additional memory accesses to the MUXSEL register(s) to put the needed DIO in the correct mode, using a different address for DOE (Formerly the Data Direction Register in the TS-7400 EP9302), using a different address for DOUT (Formerly the Data Register in the TS-7400 EP9302), and adding calls to the DIN register (Reading DIO states was achieved by reading the Data Register in the TS-7400 EP9302). Please note that each register actually has 4 addresses associated with it in order to provide atomic set/clear/toggle accesses, a read/write register (Same as standard registers in the TS-7400 EP9302), a set address, a clear address, and a toggle address. Any bits written as a 1 to the set/clear/toggle address will cause that bit to be set/cleared/toggled atomically in the register. | Code changes should not require great amounts of additional code to support the changed DIO. Differences should include mmap()ing the new base address, additional memory accesses to the MUXSEL register(s) to put the needed DIO in the correct mode, using a different address for DOE (Formerly the Data Direction Register in the TS-7400 EP9302), using a different address for DOUT (Formerly the Data Register in the TS-7400 EP9302), and adding calls to the DIN register (Reading DIO states was achieved by reading the Data Register in the TS-7400 EP9302). Please note that each register actually has 4 addresses associated with it in order to provide atomic set/clear/toggle accesses, a read/write register (Same as standard registers in the TS-7400 EP9302), a set address, a clear address, and a toggle address. Any bits written as a 1 to the set/clear/toggle address will cause that bit to be set/cleared/toggled atomically in the register. | ||
Line 442: | Line 445: | ||
==GPBUS== | ==GPBUS== | ||
At this time the GPBUS provided on the TS-7400 has not been ported over to the TS-7400_V2. This is a very simplistic bus that can easily be implemented in DIO. Contact Technologic Systems for more information on this | At this time the GPBUS provided on the TS-7400 has not been ported over to the TS-7400_V2. This is a very simplistic bus that can easily be implemented in DIO. Contact Technologic Systems for more information on this | ||
==I2C== | |||
The TS-7400 did not have a real I2C port and any use of I2C needed to be bit-banged on DIO. The TS-7400_V2 does offer a real I2C peripheral however. Existing applications using I2C would likely experience a faster and simpler migration by simply updating the codebase to continue to use the DIO bit-banging method. It will result in few lines of code and continue using an already proven out codebase. Bear in mind that timings may need to be adjusted to account for the speed increase of the TS-7400_V2 CPU. See the [[#DIO|DIO]] section for more information. | |||
==SPI== | |||
The TS-7400_V2 has one SPI port exposed on the two pin headers with one chip select under the peripheral control. If more than one chip select is needed a standard DIO may be used under software control. Note that the MISO, MOSI, and CLK pins are each available on two sets of pins while the CS line is only brought out to one. The TS-7400 shared [[#I2S|I2S]] and SPI on the same pins, on the TS-7400_V2 these two peripherals are separate. The TS-7400_V2 has a kernel module to enable the SPI port use through the standard linux SPI framework, as well as the spidev framework. It is also possible to use the SPI port by directly talking to the SPI peripheral registers in the CPU. The SPI peripheral used is SSP2 which has a base address of 0x80014000 in the i.MX286 CPU and is inside a 4kbyte address space. | |||
Code changes for basic SPI functionality should not require great amounts of additional code to support the different register layout. The SSP peripheral in the CPU supports multiple protocols, including SD/MMC/SDIO, SPI master and slave, and SSI. This means that there are only a few of the registers needed to complete SPI bus cycles. Differences should include mmap()ing the new base address, setting up the CTRL0 and CTRL1 registers, and then writing data to and reading from the DATA register. Please note that each register actually has 4 addresses associated with it in order to provide atomic set/clear/toggle accesses, a read/write register (Same as standard registers in the TS-7400 EP9302), a set address, a clear address, and a toggle address. Any bits written as a 1 to the set/clear/toggle address will cause that bit to be set/cleared/toggled atomically in the register. | |||
A code example of writing to an SPI device will be made available soon. | |||
On the TS-7400_v2 the SPI pins start up in SPI mode on port SSP2, however the kernel drivers are modularized and not loaded by default. These pins are safe to use as DIO. | |||
==UARTs== | ==UARTs== | ||
The TS-7400_V2 adds more UARTs than the original TS-7400 provids. In linux, the TTY layer takes care of all underlying peripheral and pin access for the various UARTs in the system. Currently all of the UART ports on the TS-7400_V2 start up in peripheral mode, however the kernel drivers are modularized and not loaded by default. These pins are safe to | The TS-7400_V2 adds more UARTs than the original TS-7400 provids. In linux, the TTY layer takes care of all underlying peripheral and pin access for the various UARTs in the system. Currently all of the UART ports on the TS-7400_V2 start up in peripheral mode, however the kernel drivers are modularized and not loaded by default. These pins are safe to use as DIO. In order to change the number of UARTs used by the driver or to make any modifications to the pin muxes or startup states, the kernel will need to be modified. The TS-7400_V2 has a Debug UART that is always intended to be such, in addition to that there are 4 UARTs for a total of 5; the TS-7400 only has 3 UARTs total. Please note that the TS-7400 used UART0 in two places on the pin headers, the TS-7400_V2 replaces one of these with the Debug UART and UART0 is a separate device. All UARTs in the TS-7400_V2 are CPU UARTs. Also note that UART2 does not offer an automatic TXEN on the TS-7400_V2, there is a DIO pin there in its place that can be used as a TXEN. | ||
Code changes should only require changing the device name of the UART(s) used. The setup steps for configuring the port itself will likely require no changes. See the [[#pin-by-pin comparison|comparison]] to identify which pins are being used by which UARTs. | Code changes should only require changing the device name of the UART(s) used. The setup steps for configuring the port itself will likely require no changes. See the [[#pin-by-pin comparison|comparison]] to identify which pins are being used by which UARTs. |
Revision as of 14:59, 18 September 2013
Migration
The i.MX286 based TS-7400_V2 is designed as a direct upgrade path from the EP9302 based TS-7400. While these SBCs have the same form factor and a very identical pinout, there are a few software concerns that need to be addressed. Since the TS-7400_V2 utilizes a different CPU than the TS-7400, accessing any of the DIO or peripherals directly though memory mapped addresses will require code differences between the two SBCs. Pinouts are matched as best as possible between the two SBCs, however some pins may not apply from one to the other. This makes for a minor amount of hardware differences which may affect your upgrade. This guide is intended to provide details in differences between the TS-7400 and TS-7400_V2, for both hardware and software. This guide will also link to relevant sections of the TS-7400_V2 manual for more in-depth information on software and hardware ports.
Pin-by-pin comparison
Upper header pin-out (26-pin)
TS-7400 | TS-7400_V2 | |||
---|---|---|---|---|
Pin # | Name | Function | Name | Function |
1 | TDO | TS Production Reserved | I2C_DAT | CPU DIO3_25 or I2C Data |
2 | TMS | TS Production Reserved | SD_BOOT# | Boot mode pin (SD or NAND) |
3 | GND | Ground | GND | Ground |
4 | TDI | TS Production Reserved | GND | Ground |
5 | BLAST_BOOT# | Blast boot (9441 boot) | FPGA_DIO_0 | DIO (Will change in next rev) |
6 | TCK | TS Production Reserved | I2C_CLK | CPU DIO3_24 or I2C Clock |
7 | UART0_TXD | UART0 TXD | DEBUG_TXD | Debug UART TXD |
8 | UART0_RXD | UART0 RXD | DEBUG_RXD | Debug UART RX |
9 | SPI_MISO | SPI MISO | SPI_MISO [1] | CPU DIO2_04 or SPI MISO |
10 | 3.3V | 3.3V Output | 3.3V | 3.3V Output |
11 | BLAST_EE_CS# | Chip select 9441 flash | FPGA_DIO_1 | DIO (Will change in next rev) |
12 | SPI_MOSI | SPI MOSI | SPI_MOSI [1] | CPU DIO2_06 or SPI MOSI |
13 | FLASH_CS# | Chip select 9441 EEPROM | FPGA_DIO_2 | DIO (Will change in next rev) |
14 | SPI_CLK | SPI clock output | SPI_CLK [1] | CPU DIO2_07 or SPI clock |
15 | 5V | 5V regulated power input | 5V | 5V regulated power input |
16 | EXT_RESET# | External reset input | HARD_REBOOT# | External reset input |
17 | BLAST_PRESENT# | Boot hijacker present input | FPGA_DIO_3 | DIO (Will change in next rev) |
18 | GND | Ground | GND | Ground |
19 | PORTB_4 | CPU DIO | DIO_19 | CPU DIO1_24 |
20 | GND | Ground | GND | Ground |
21 | EN_5V | Switching power supply en | FPGA_DIO_04 | DIO (Will change in next rev) |
22 | EP_USB+ | EP93xx USB data | USB_OTG_P | i.MX286 USB OTG data |
23 | FIL_VIN | Reserved | FPGA_DIO_5 | DIO (Will change in next rev) |
24 | EP_USB- | EP93xx USB data | USB_OTG_M | i.MX286 USB OTG data |
25 | PORTB_7 | CPU DIO | DIO_25 | CPU DIO1_25 |
26 | USB_5V | USB 5V power | USB_SW_5V | Switched USB 5V power |
Lower header pin-put (40-pin)
TS-7400 | TS-7400_V2 | |||
---|---|---|---|---|
Pin # | Name | Function | Name | Function |
1 | DIO_00 | GPIO0 or GPBUS AD0 | DIO_00 | CPU DIO1_16 |
2 | 3.3V | 3.3V Output | 3.3V | 3.3V Output |
3 | DIO_01 | GPIO1 or GPBUS AD1 | DIO_01 | CPU DIO1_17 |
4 | DIO_02 | GPIO2 or GPBUS AD2 | DIO_02 | CPU DIO1_18 |
5 | DIO_03 | GPIO3 or GPBUS AD3 | DIO_03 | CPU DIO1_19 |
6 | DIO_04 | GPIO4 or GPBUS AD4 | DIO_04 | CPU DIO1_20 |
7 | DIO_05 | GPIO5 or GPBUS AD5 | DIO_05 | CPU DIO1_21 |
8 | DIO_06 | GPIO6 or GPBUS AD6 | DIO_06 | CPU DIO1_22 |
9 | DIO_07 | GPIO7 or GPBUS AD7 | DIO_07 | CPU DIO1_23 |
10 | DIO_08 | GPIO8 or GPBUS ALE | DIO_08 | CPU DIO1_15 |
11 | DIO_09 | GPIO9 or GPBUS RD | DIO_09 | CPU DIO1_14 |
12 | GND | Ground | GND | Ground |
13 | DIO_10 | GPIO10 or GPBUS WR | CAN_RX0 | CPU DIO3_13 or CAN RX0 |
14 | DIO_11 | GPIO11 or GPBUS IRQ | CAN_RX1 | CPU DIO3_15 or CAN RX1 |
15 | DIO_15 | GPIO12 or GPBUS DRQ | CAN_TX0 | CPU DIO3_12 or CAN TX0 |
16 | DIO_13 | GPIO13 or GPBUS 14.7456Mhz | CAN_TX1 | CPU DIO3_14 or CAN TX1 |
17 | DIO_14 | GPIO14 | UART3_TXD | CPU DIO2_19 or UART3 |
18 | 5V | 5V regulated power input/output | 5V | 5V regulated power input |
19 | DIO_15 | GPIO15 or UART2 TXEN | DIO_15 | CPU DIO3_29 or PWM4 |
20 | DIO_16 | GPIO16 or UART2 RXD | UART2_RXD | CPU DIO2_16 or UART2 |
21 | DIO_17 | GPIO17 or UART2 TXD | UART2_TXD | CPU DIO2_17 or UART2 |
22 | DIO_18 | GPIO18 or UART0 TXD | UART0_TXD | CPU DIO3_01 or UART0 |
23 | DIO_19 | GPIO19 or UART0 RXD | UART0_RXD | CPU DIO3_00 or UART0 |
24 | UART1_RXD | UART1 RXD | UART1_RXD | CPU DIO3_04 or UART1 |
25 | UART1_TXD | UART1 TXD | UART1_TXD | CPU DIO3_05 or UART1 |
26 | 1.8V | 1.8V | UART3_RXD | CPU DIO2_18 or UART3 |
27 | ADC0 | EP93xx ADC0 | ADC0 | i.MX286 LRADC0 |
28 | ADC1 | EP93xx ADC1 | ADC1 | i.MX286 LRADC1 |
29 | ADC2 | EP93xx ADC2 | ADC2 | i.MX286 LRADC2 |
30 | ADC3 | EP93xx ADC3 | ADC3 | i.MX283 LRADC3 |
31 | GND | Ground | GND | Ground |
32 | ABIT_CLK | EP93xx CPU AC97 | I2S_BIT_CLK | CPU DIO3_22 or I2S Clock |
33 | ASDO | EP93xx CPU AC97 | I2S_TXD | CPU DIO3_23 or I2S TXD |
34 | ASYNCH | EP93xx CPU AC97 | I2S_FRAME | CPU DIO3_21 or I2S Frame |
35 | ARST# | EP93xx CPU AC97 | I2S_MCLK | CPU DIO3_20 or I2S MCLK |
36 | ASDI | EP93xx CPU AC97 | I2S_RXD | CPU DIO3_26 or I2S RXD |
37 | SSP_TX | EP93xx SPI/SSP/I2S signal | SPI_MOSI [1] | CPU DIO2_06 or SPI MOSI |
38 | SSP_RX | EP93xx SPI/SSP/I2S signal | SPI_MISO [1] | CPU DIO2_04 or SPI MISO |
39 | SSP_FRM | EP93xx SPI/SSP/I2S signal | SPI_CS# [1] | CPU DIO2_05 or SPI Chip select |
40 | SSP_CLK | EP93xx SPI/SSP/I2S signal | SPI_CLK [1] | CPU DIO2_07 or SPI clock |
Peripheral Functions
AC'97
The TS-7400_V2 does not offer an AC'97 audio port. Audio functionality can still be achieved by using I2S audio.
DIO
There are a few fundamental differences between DIO access on the TS-7400 and the TS-7400_V2. On the TS-7400_V2 nearly every pin has multiple functions associated with it, one of them being DIO, and one to three of them being other CPU peripherals. This mux must be set to DIO mode before a pin can be utilized as a DIO. The TS-7400 refers to different DIO clusters as "Ports" that are then subdivided in to pins, i.e. PORTA_1, PORTB_7, etc. The TS-7400_V2 has groupings of all pins held in "Banks" that are subdivided in to pins, i.e. DIO3_20, DIO2_16, etc. The bank and pin number are important to driving the correct DIO pin. All DIO and its associated registers are able to be accessed at base 0x80018000 with all resisters residing within a 4kbyte address space. IRQ settings start at 0x80019000 and are also within a 4kbyte address space, however these registers should not normally need to be modified; any changes to IRQs and their settings should be made in-kernel.
Code changes should not require great amounts of additional code to support the changed DIO. Differences should include mmap()ing the new base address, additional memory accesses to the MUXSEL register(s) to put the needed DIO in the correct mode, using a different address for DOE (Formerly the Data Direction Register in the TS-7400 EP9302), using a different address for DOUT (Formerly the Data Register in the TS-7400 EP9302), and adding calls to the DIN register (Reading DIO states was achieved by reading the Data Register in the TS-7400 EP9302). Please note that each register actually has 4 addresses associated with it in order to provide atomic set/clear/toggle accesses, a read/write register (Same as standard registers in the TS-7400 EP9302), a set address, a clear address, and a toggle address. Any bits written as a 1 to the set/clear/toggle address will cause that bit to be set/cleared/toggled atomically in the register.
On the TS-7400_V2 most pins start up in DIO while others are in peripheral. Those that start up in a peripheral mode will likely have a kernel driver associated with them. Changing the MUXSEL bits of any pin that is a peripheral may result in system instability, loss of peripheral functionality, or the associated MUXSEL register being set back in to peripheral mode by the driver with no warning. Please verify that any pin(s) to be used do not have a loaded and running kernel module to support a peripheral used on the aforementioned pin(s).
Each pin is also interrupt capable. Combined with our userspace IRQs, it allows interrupt driven userspace applications to be written very easily.
See the TS-7400_V2 manual and the i.MX28 manual for more information.
GPBUS
At this time the GPBUS provided on the TS-7400 has not been ported over to the TS-7400_V2. This is a very simplistic bus that can easily be implemented in DIO. Contact Technologic Systems for more information on this
I2C
The TS-7400 did not have a real I2C port and any use of I2C needed to be bit-banged on DIO. The TS-7400_V2 does offer a real I2C peripheral however. Existing applications using I2C would likely experience a faster and simpler migration by simply updating the codebase to continue to use the DIO bit-banging method. It will result in few lines of code and continue using an already proven out codebase. Bear in mind that timings may need to be adjusted to account for the speed increase of the TS-7400_V2 CPU. See the DIO section for more information.
SPI
The TS-7400_V2 has one SPI port exposed on the two pin headers with one chip select under the peripheral control. If more than one chip select is needed a standard DIO may be used under software control. Note that the MISO, MOSI, and CLK pins are each available on two sets of pins while the CS line is only brought out to one. The TS-7400 shared I2S and SPI on the same pins, on the TS-7400_V2 these two peripherals are separate. The TS-7400_V2 has a kernel module to enable the SPI port use through the standard linux SPI framework, as well as the spidev framework. It is also possible to use the SPI port by directly talking to the SPI peripheral registers in the CPU. The SPI peripheral used is SSP2 which has a base address of 0x80014000 in the i.MX286 CPU and is inside a 4kbyte address space.
Code changes for basic SPI functionality should not require great amounts of additional code to support the different register layout. The SSP peripheral in the CPU supports multiple protocols, including SD/MMC/SDIO, SPI master and slave, and SSI. This means that there are only a few of the registers needed to complete SPI bus cycles. Differences should include mmap()ing the new base address, setting up the CTRL0 and CTRL1 registers, and then writing data to and reading from the DATA register. Please note that each register actually has 4 addresses associated with it in order to provide atomic set/clear/toggle accesses, a read/write register (Same as standard registers in the TS-7400 EP9302), a set address, a clear address, and a toggle address. Any bits written as a 1 to the set/clear/toggle address will cause that bit to be set/cleared/toggled atomically in the register.
A code example of writing to an SPI device will be made available soon.
On the TS-7400_v2 the SPI pins start up in SPI mode on port SSP2, however the kernel drivers are modularized and not loaded by default. These pins are safe to use as DIO.
UARTs
The TS-7400_V2 adds more UARTs than the original TS-7400 provids. In linux, the TTY layer takes care of all underlying peripheral and pin access for the various UARTs in the system. Currently all of the UART ports on the TS-7400_V2 start up in peripheral mode, however the kernel drivers are modularized and not loaded by default. These pins are safe to use as DIO. In order to change the number of UARTs used by the driver or to make any modifications to the pin muxes or startup states, the kernel will need to be modified. The TS-7400_V2 has a Debug UART that is always intended to be such, in addition to that there are 4 UARTs for a total of 5; the TS-7400 only has 3 UARTs total. Please note that the TS-7400 used UART0 in two places on the pin headers, the TS-7400_V2 replaces one of these with the Debug UART and UART0 is a separate device. All UARTs in the TS-7400_V2 are CPU UARTs. Also note that UART2 does not offer an automatic TXEN on the TS-7400_V2, there is a DIO pin there in its place that can be used as a TXEN.
Code changes should only require changing the device name of the UART(s) used. The setup steps for configuring the port itself will likely require no changes. See the comparison to identify which pins are being used by which UARTs.
Port | TS-7400 name | TS-7400_V2 name |
---|---|---|
Debug UART | /dev/ttyAM0 | |
UART0 | /dev/ttyAM0 | /dev/ttySP0 |
UART1 | /dev/ttyAM1 | /dev/ttySP1 |
UART2 | /dev/ttyTS0 | /dev/ttySP2 |
UART3 | /dev/ttySP3 |