TS-7600 I2C: Difference between revisions
From embeddedTS Manuals
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A standard two-wire I2C interface is provided on this SBC. The i.MX28 CPU has I2C hardware to communicate with devices on the bus. The hardware is able to be accessed from userspace with the linux i2c-dev interface. On this SBC the I2C pins from the CPU are connected to the on-board RTC, and then brought out to external pins. See the [[# | A standard two-wire I2C interface is provided on this SBC. The i.MX28 CPU has I2C hardware to communicate with devices on the bus. The hardware is able to be accessed from userspace with the linux i2c-dev interface. On this SBC the I2C pins from the CPU are connected to the on-board RTC, and then brought out to external pins. See the [[#DIO|External Interfaces]] section for the location of these signals. | ||
The RTC on the SBC uses two different addresses, one for the actual RTC registers, the other for the RTC's onboard NVRAM. | The RTC on the SBC uses two different addresses, one for the actual RTC registers, the other for the RTC's onboard NVRAM. | ||
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Outside of those addresses, no other I2C addresses are in use on this SBC. | Outside of those addresses, no other I2C addresses are in use on this SBC. | ||
For more information on the i.MX28 I2C implementation, see the [ | For more information on the i.MX28 I2C implementation, see the [https://www.nxp.com/docs/en/reference-manual/MCIMX28RM.pdf CPU manual]. | ||
Latest revision as of 14:47, 29 June 2020
A standard two-wire I2C interface is provided on this SBC. The i.MX28 CPU has I2C hardware to communicate with devices on the bus. The hardware is able to be accessed from userspace with the linux i2c-dev interface. On this SBC the I2C pins from the CPU are connected to the on-board RTC, and then brought out to external pins. See the External Interfaces section for the location of these signals.
The RTC on the SBC uses two different addresses, one for the actual RTC registers, the other for the RTC's onboard NVRAM.
| Address | Function |
|---|---|
| 0x6F | RTC |
| 0x57 | NVRAM |
Outside of those addresses, no other I2C addresses are in use on this SBC.
For more information on the i.MX28 I2C implementation, see the CPU manual.