TS-7970 FPGA Changelog

Check the FPGA rev with:

echo $(($(tshwctl --peek --addr 51)>>4))

Rev	Changes
0	Initial Release
1	Switched max3100 to use FPGA_IRQ_1 to leave FPGA_IRQ_0 to the silabs.
2	Corrected CTS/RTS polarity on MAX3100 Corrected flipped CPU UART CTS/RTS for bluetooth Corrected HD1 SPI bus
3	Disabled pulldown on HD1 SPI CS.
4	Fixed the FPGA ttyMAX* uarts
5	The signal FPGA_IRQ_0 is now FPGA_RESET which needs to be pulsed on reset by u-boot. This is implemented in the May-27-2016 release. Register 61, bit 1 is now used to force SPI at all times on the HD1 SPI pins rather than just on chip select assert. This should allow any GPIO to be used as chip selects.
6	Disables USB HUB 24mhz while in reset
7	Includes support for REV D pin changes.
11	Fix for CPU UART TXEN behavior. ttyMAX uarts are not affected.
12	Migrated to Mach XO3

Using the u-boot from Oct-07-2015 or later you can reload the FPGA during startup for custom FPGAs. During startup you will see u-boot reload this file:

Bytes transferred = 56341 (dc15 hex)
VME file checked: starting downloading to FPGA
Diamond Deployment Tool 3.5
CREATION DATE: Wed Oct 07 11:38:24 2015


Downloading FPGA 53248/56341 completed
FPGA downloaded successfully