TS-7970 FPGA Sections

The Lattice ICE40 FPGA provides auto TX enable for RS-485 half duplex, a few more DIO, a crossbar, and it can generate clocks for use on a baseboard. Most of these registers are controlled using tshwctl in the ts4900-utils repository. The DIO can be accessed using the sysfs GPIOs 224 to 255 using the "ts4900gpio" driver. See the #GPIO section for more information on the recommended GPIO access.

Usage: tshwctl [OPTIONS] ...
Technologic Systems TS-4900 Utility
     -m, --addr <address>   Sets up the address for a peek/poke
     -v, --poke <value>     Writes the value to the specified address
     -t, --peek             Reads from the specified address
     -i, --mode <8n1>       Used with -a, sets mode like '8n1', '7e2', etc
     -x, --baud <speed>     Used with -a, sets baud rate for auto485
     -a, --autotxen <uart>  Enables autotxen for supported CPU UARTs
                              Uses baud/mode if set or reads the current
                              configuration of that uart
     -c, --dump             Prints out the crossbar configuration
     -g, --get              Print crossbar for use in eval
     -s, --set              Read environment for crossbar changes
     -q, --showall          Print all possible FPGA inputs and outputs.
     -h, --help             This message

Addr	Bits	Function
00	2:0	Reserved
	7:3	TTYMXC2_RXD Crossbar
01	2:0	Reserved
	7:3	TTYMXC4_RXD Crossbar
02	0	TTYMXC2_CTS Output Enable
	1	TTYMXC2_CTS Output Data
	2	TTYMXC2_CTS Input Data
	7:3	CN1_87 Crossbar
03	0	TTYMXC3_RXD Output Enable
	1	TTYMXC3_RXD Output Data
	2	TTYMXC3_RXD Input Data
	7:3	TTYMXC3_RXD Crossbar
04	0	TTYMXC1_CTS Output Enable
	1	TTYMXC1_CTS Output Data
	2	TTYMXC1_CTS Input Data
	7:3	TTYMXC1_CTS Crossbar
05	0	TTYMXC2_RTS Output Enable
	1	TTYMXC2_RTS Output Data
	2	TTYMXC2_RTS Input Data
	7:3	TTYMXC2_RTS Crossbar
06	0	MB_TXD Output Enable
	1	MB_TXD Output Data
	2	MB_TXD Input Data
	7:3	MB_TXD Crossbar
07	0	MB_TX_EN_485 Output Enable
	1	MB_TX_EN_485 Output Data
	2	MB_TX_EN_485 Input Data
	7:3	MB_TX_EN_485 Crossbar
08	0	STC_TXD_485 Output Enable
	1	STC_TXD_485 Output Data
	2	STC_TXD_485 Input Data
	7:3	STC_TXD_485 Crossbar
09	0	STC_TX_EN_485 Output Enable
	1	STC_TX_EN_485 Output Data
	2	STC_TX_EN_485 Input Data
	7:3	STC_TX_EN_485 Crossbar
10	0	TXD_232_COM Output Enable
	1	TXD_232_COM Output Data
	2	TXD_232_COM Input Data
	7:3	TXD_232_COM Crossbar
11	0	RTS_232_COM Output Enable
	1	RTS_232_COM Output Data
	2	RTS_232_COM Input Data
	7:3	RTS_232_COM Crossbar
12	0	HD1_TXD Output Enable
	1	HD1_TXD Output Data
	2	HD1_TXD Input Data
	7:3	HD1_TXD Crossbar
13	0	BT_EN Output Enable
	1	BT_EN Output Data
	2	BT_EN Input Data
	7:3	BT_EN Crossbar	14	0	WL_EN Output Enable
1	WL_EN Output Data
2	WL_EN Input Data
7:3	WL_EN Crossbar
15	0:1	Reserved
	2	BT_RTS Input Data
	7:3	Reserved
16	0	BT_CTS Output Enable
	1	BT_CTS Output Data
	2	WL_EN Input Data
	7:3	WL_EN Crossbar

The FPGA crossbar allows almost any of the FPGA pins to be rerouted on the carrier board. All of the above registers that have a crossbar mux value can be written with these values to change the output value. When using the crossbar pins that are outputs, bit 1 should also be set to allow output enables.

Crossbar Value	Selected Function
0	Do not change
1	BT_RTS
2	BT_TXD
3	CN1_63
4	CN1_67
5	CN2_100
6	ttymxc1 RTS#
7	CN2_78
8	CN2_80
9	CN2_86
10	CN2_88
11	CN2_94
12	CN2_96
13	CN2_98
14	ttymxc3 TXD
15	ttymxc1 TXD
16	SPIUART0_TX
17	SPIUART0_TXEN
18	SPIUART0_RTS
19	SPIUART1_TX
20	SPIUART1_TXEN
21	SPIUART1_RTS
22	SPIUART2_TX
23	SPIUART2_TXEN
24	SPIUART2_RTS
25	ttymxc1 TXEN
26	ttymxc3 TXEN
27	12MHz clock
28	14MHz clock
29	24MHz clock
30	28.88MHz clock
31	GPIO

On startup these are the default values:

Pad	Default Mapping	FGPA Addr	Crossbar Reset Value