TS-7970 FPGA Sections: Difference between revisions
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| rowspan=3 | 29 | | rowspan=3 | 29 | ||
| 7: | | 7:2 | ||
| Reserved | | Reserved | ||
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| | | 1 | ||
| push_sw reset <ref> If this is set to 1, then when SW1 is pressed a hardware reboot will happen </ref> | | push_sw reset <ref> If this is set to 1, then when SW1 is pressed a hardware reboot will happen </ref> | ||
|- | |- | ||
| | | 0 | ||
| Reserved | | Reserved | ||
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| rowspan=3 | 31 | | rowspan=3 | 31 | ||
| 7: | | 7:3 | ||
| Reserved | | Reserved | ||
|- | |- | ||
| | | 2 | ||
| Push SW Input Data | | Push SW Input Data | ||
|- | |- | ||
| 0 | | 1:0 | ||
| Reserved | | Reserved | ||
|- | |- |
Revision as of 13:07, 4 September 2018
The Lattice MachXO2 FPGA provides several features used by default on the TS-7970:
- auto TX enable for RS-485 half duplex
- DIO expander
- UART/DIO crossbar
- Clock generator
It is also software reloadable and can be customized for specific purposes. The registers are accessed over I2C using the "tshwctl" utility in the ts4900-utils repository. The DIO can be accessed using the sysfs GPIOs 224 to 288 using the "tsgpio" driver. See the #GPIO section for more information on the recommended GPIO access.
Usage: tshwctl [OPTIONS] ... Technologic Systems i.mx6 FPGA Utility -m, --addr <address> Sets up the address for a peek/poke -v, --poke <value> Writes the value to the specified address -t, --peek Reads from the specified address -i, --mode <8n1> Used with -a, sets mode like '8n1', '7e2', etc -x, --baud <speed> Used with -a, sets baud rate for auto485 -a, --autotxen <uart> Enables autotxen for supported CPU UARTs Uses baud/mode if set or reads the current configuration of that uart -c, --dump Prints out the crossbar configuration -g, --get Print crossbar for use in eval -s, --set Read environment for crossbar changes -q, --showall Print all possible FPGA inputs and outputs. -h, --help This message
Addr | Bits | Function |
---|---|---|
00 | 7:2 | TTYMXC2_RXD Crossbar |
1 | Reserved | |
0 | TTYMXC2_RXD Output Enable | |
01 | 7:2 | TTYMXC4_RXD Crossbar |
1 | Reserved | |
0 | TTYMXC4_RXD Output Enable | |
02 | 7:2 | TTYMXC2_RTS Crossbar |
1 | TTYMXC2_RTS Data | |
0 | TTYMXC2_RTS Output Enable | |
03 | 7:2 | TTYMXC3_RXD Crossbar |
1 | Reserved | |
0 | TTYMXC3_RXD Output Enable | |
04 | 7:2 | TTYMXC1_CTS Crossbar |
1 | Reserved | |
0 | TTYMXC1_CTS Output Enable | |
05 | 7:2 | TTYMXC2_CTS Crossbar |
1 | TTYMXC2_CTS Output Data | |
0 | TTYMXC2_CTS Output Enable | |
06 | 7:2 | MB_TXD Crossbar |
1 | Reserved | |
0 | MB_TXD Output Enable | |
07 | 7:2 | MB_TX_EN_485 Crossbar |
1 | Reserved | |
0 | MB_TX_EN_485 Output Enable | |
08 | 7:2 | STC_TXD_485 Crossbar |
1 | Reserved | |
0 | STC_TXD_485 Output Enable | |
09 | 7:2 | STC_TX_EN_485 Crossbar |
1 | Reserved | |
0 | STC_TX_EN_485 Output Enable | |
10 | 7:2 | TXD_232_COM Crossbar |
1 | Reserved | |
0 | TXD_232_COM Output Enable | |
11 | 7:2 | RTS_232_COM Crossbar |
1 | Reserved | |
0 | RTS_232_COM Output Enable | |
12 | 7:2 | HD1_TXD Crossbar |
1 | HD1_TXD Data | |
0 | HD1_TXD Output Enable | |
13 | 7:2 | Reserved |
1 | BT_EN Data | |
0 | BT_EN Output Enable | |
14 | 7:2 | Reserved |
1 | WL_EN Data | |
0 | WL_EN Output Enable | |
15 | 7:3 | Reserved |
2 | BT_RTS Input Data | |
1:0 | Reserved | |
16 | 7:2 | BT_CTS Crossbar |
1 | BT_CTS Data | |
0 | BT_CTS Output Enable | |
17 | 7:2 | BT_RXD Crossbar |
1:0 | Reserved | |
18 | 7:2 | TTYMXC1_RXD Crossbar |
1:0 | Reserved | |
19 | 7:2 | HD1_DIO_1 Crossbar |
1 | HD1_DIO_1 Data | |
0 | HD1_DIO_1 Output Enable | |
20 | 7:2 | HD1_DIO_2 Crossbar |
1 | HD1_DIO_2 Data | |
0 | HD1_DIO_2 Output Enable | |
21 | 7:2 | HD1_DIO_3 Crossbar |
1 | HD1_DIO_3 Data | |
0 | HD1_DIO_3 Output Enable | |
22 | 7:2 | HD1_DIO_4 Crossbar |
1 | HD1_DIO_4 Data | |
0 | HD1_DIO_4 Output Enable | |
23 | 7:2 | HD1_DIO_5 Crossbar |
1 | HD1_DIO_5 Data | |
0 | HD1_DIO_5 Output Enable | |
24 | 7:2 | HD1_DIO_6 Crossbar |
1 | HD1_DIO_6 Data | |
0 | HD1_DIO_6 Output Enable | |
25 | 7:2 | EN_OUT_1 Crossbar |
1 | EN_OUT_1 Data | |
0 | EN_OUT_1 Output Enable | |
26 | 7:2 | EN_OUT_2 Crossbar |
1 | EN_OUT_2 Data | |
0 | EN_OUT_2 Output Enable | |
27 | 7:2 | FPGA_IRQ_1 Crossbar |
1 | Input Data | |
0 | Reserved | |
28 | 7:2 | STC_TXD_232 Crossbar |
1:0 | Reserved | |
29 | 7:2 | Reserved |
1 | push_sw reset [1] | |
0 | Reserved | |
30 | 7:2 | Reserved |
1 | Reboot (on 1) [2] | |
0 | Reserved | |
31 | 7:3 | Reserved |
2 | Push SW Input Data | |
1:0 | Reserved | |
32 | 7:0 | RS485_CNT0 [23:16] |
33 | 7:0 | RS485_CNT0 [15:8] |
34 | 7:0 | RS485_CNT0 [7:0] |
35 | 7:0 | RS485_CNT1 [23:16] |
36 | 7:0 | RS485_CNT1 [15:8] |
37 | 7:0 | RS485_CNT1 [7:0] |
38 | 7:0 | RS485_CNT2 [23:16] |
39 | 7:0 | RS485_CNT2 [15:8] |
40 | 7:0 | RS485_CNT2 [7:0] |
41 | 7:0 | RS485_CNT3 [23:16] |
42 | 7:0 | RS485_CNT3 [15:8] |
43 | 7:0 | RS485_CNT3 [7:0] |
44 | 7:2 | TTYMAX0_RXD Crossbar |
1 | Reserved | |
0 | TTYMAX0_RXD Output Enable | |
45 | 7:2 | TTYMAX1_RXD Crossbar |
1 | Reserved | |
0 | TTYMAX1_RXD Output Enable | |
46 | 7:2 | TTYMAX2_RXD Crossbar |
1 | Reserved | |
0 | TTYMAX2_RXD Output Enable | |
51 | 7:4 | FPGA Revision |
3 | R39 Option Resistor (1 = not present) | |
2 | R34 Option Resistor (1 = not present) | |
1 | R36 Option Resistor (1 = not present) | |
0 | R37 Option Resistor (1 = not present) | |
53 | 7:2 | TTYMAX0_CTS Crossbar |
1 | Reserved | |
0 | TTYMAX0_CTS Output Enable | |
54 | 7:2 | TTYMAX1_CTS Crossbar |
1 | Reserved | |
0 | TTYMAX1_CTS Output Enable | |
55 | 7:2 | TTYMAX2_CTS Crossbar |
1 | Reserved | |
0 | TTYMAX2_CTS Output Enable | |
56 | 7:6 | DIO1 and DIO2 input data. |
5:0 | HD1_DIO input data | |
57 | 7:2 | Reserved |
1 | LCD_D10 | |
0 | CN_99_BOOT_SEL Input Data | |
58 | 7:2 | HD1_SPI_CLK Crossbar |
1 | HD1_SPI_CLK Data | |
0 | HD1_SPI_CLK Output Enable | |
59 | 7:2 | HD1_SPI_MOSI Crossbar |
1 | HD1_SPI_MOSI Data | |
0 | HD1_SPI_MOSI Output Enable | |
60 | 7:2 | HD1_SPI_MISO Crossbar |
1 | HD1_SPI_MISO Data | |
0 | HD1_SPI_MISO Output Enable | |
61 | 7:2 | Reserved |
1 | 1 = Always pass through SPI rather than on HD1_SPI_CS# assert only | |
0 | Reserved |
FPGA Crossbar
The FPGA crossbar allows almost any of the FPGA pins to be rerouted. All the FPGA addresses that have a crossbar mux register can be written with these output values.
Crossbar Value | Selected Function |
---|---|
0 | Do not change |
1 | BT_RTS |
2 | BT_TXD |
3 | TTYMXC4_TXD |
4 | TTYMXC2_TXD |
5 | TTYMXC2_RTS |
6 | TTYMXC1_RTS |
7 | TTYMXC2_CTS |
8 | MB_RXD_485 |
9 | STC_RXD_485_3V |
10 | RXD_232_COM |
11 | CTS_232_COM |
12 | STC_RXD |
13 | HD1_RXD |
14 | TTYMXC3_TXD |
15 | TTYMXC1_TXD |
16 | TTYMAX0_TXD |
17 | TTYMAX0_TXEN |
18 | TTYMAX0_RTS |
19 | TTYMAX1_TXD |
20 | TTYMAX1_TXEN |
21 | TTYMAX1_RTS |
22 | TTYMAX2_TXD |
23 | TTYMAX2_TXEN |
24 | TTYMAX2_RTS |
25 | TTYMXC1_TXEN |
26 | TTYMXC3_TXEN |
27 | CLK_12MHZ |
28 | CLK_14MHZ |
29 | FPGA_24MHZ_CLK |
30 | CLK_28MHZ |
31 | GPIO |
32 | HD1_DIO_1 |
33 | HD1_DIO_2 |
34 | HD1_DIO_3 |
35 | HD1_DIO_4 |
36 | HD1_DIO_5 |
37 | HD1_DIO_6 |
38 | DIO_1_IN |
39 | DIO_2_IN |
40 | LCD_D10 |
41 | PUSH_SW_CPU |
42 | HD1_SPI_CLK |
43 | HD1_SPI_MOSI |
44 | HD1_SPI_MISO |
For example, we can remap three ttyMAX ports to the HD1 GPIO.
Pin | Function |
---|---|
HD1_DIO_1 | ttyMAX0 txd |
HD1_DIO_2 | ttyMAX0 rxd |
HD1_DIO_3 | ttyMAX1 txd |
HD1_DIO_4 | ttyMAX1 rxd |
HD1_DIO_5 | ttyMAX2 txd |
HD1_DIO_6 | ttyMAX2 rxd |
tshwctl --dump
This will return the mapping of all of the pins as they are currently set. These are the relevant pins:
FPGA Pad (DIR) (VAL) FPGA Output MB_TXD ( in) ( 0) TTYMAX1_TXD STC_TXD_485 ( in) ( 0) TTYMAX0_TXD RTS_232_COM ( in) ( 0) TTYMAX2_TXD HD1_DIO_1 ( in) ( 0) GPIO HD1_DIO_2 ( in) ( 0) GPIO HD1_DIO_3 ( in) ( 0) GPIO HD1_DIO_4 ( in) ( 0) GPIO HD1_DIO_5 ( in) ( 0) GPIO HD1_DIO_6 ( in) ( 0) GPIO TTYMAX0_RXD ( in) ( 0) STC_RXD_485_3V TTYMAX1_RXD ( in) ( 0) MB_RXD_485 TTYMAX2_RXD ( in) ( 0) CTS_232_COM ...
The tshwctl tool uses the bash environment to set/get pin status. To remap these pins:
eval $(tshwctl --get)
export HD1_DIO_1=TTYMAX0_TXD
export HD1_DIO_3=TTYMAX1_TXD
export HD1_DIO_5=TTYMAX2_TXD
export TTYMAX0_RXD=HD1_DIO_2
export TTYMAX1_RXD=HD1_DIO_4
export TTYMAX2_RXD=HD1_DIO_6
# These last 3 aren't required, but this will disable ttyMAX pins on
# their default locations. Without this, writes to /dev/ttyMAX0
# would go to both STC_TXD_485 and to HD1_DIO_1.
export MB_TXD=GPIO
export STC_TXD_485=GPIO
export RTS_232_COM=GPIO
# This will read the environment and look for the PAD names
# for any changes and apply them.
tshwctl --set