TS-7970 FPGA Sections

The Lattice ICE40 FPGA provides auto TX enable for RS-485 half duplex, a few more DIO, a crossbar, and it can generate clocks for use on a baseboard. Most of these registers are controlled using tshwctl in the ts4900-utils repository. The DIO can be accessed using the sysfs GPIOs 224 to 255 using the "ts4900gpio" driver. See the #GPIO section for more information on the recommended GPIO access.

Usage: tshwctl [OPTIONS] ...
Technologic Systems i.mx6 FPGA Utility
     -m, --addr <address>   Sets up the address for a peek/poke
     -v, --poke <value>     Writes the value to the specified address
     -t, --peek             Reads from the specified address
     -i, --mode <8n1>       Used with -a, sets mode like '8n1', '7e2', etc
     -x, --baud <speed>     Used with -a, sets baud rate for auto485
     -a, --autotxen <uart>  Enables autotxen for supported CPU UARTs
                              Uses baud/mode if set or reads the current
                              configuration of that uart
     -c, --dump             Prints out the crossbar configuration
     -g, --get              Print crossbar for use in eval
     -s, --set              Read environment for crossbar changes
     -q, --showall          Print all possible FPGA inputs and outputs.
     -h, --help             This message

Addr	Bits	Function
00	0	TTYMXC2_RXD Output Enable
	1	Reserved
	7:2	TTYMXC2_RXD Crossbar
01	0	TTYMXC4_RXD Output Enable
	1	Reserved
	7:2	TTYMXC4_RXD Crossbar
02	0	TTYMXC2_CTS Output Enable
	1	TTYMXC2_CTS Data
	7:2	TTYMXC2_CTS Crossbar
03	0	TTYMXC3_RXD Output Enable
	1	Reserved
	7:2	TTYMXC3_RXD Crossbar
04	0	TTYMXC1_CTS Output Enable
	1	Reserved
	7:2	TTYMXC1_CTS Crossbar
05	0	TTYMXC2_RTS Output Enable
	1	TTYMXC2_RTS Output Data
	7:2	TTYMXC2_RTS Crossbar
06	0	MB_TXD Output Enable
	1	Reserved
	7:2	MB_TXD Crossbar
07	0	MB_TX_EN_485 Output Enable
	1	Reserved
	7:2	MB_TX_EN_485 Crossbar
08	0	STC_TXD_485 Output Enable
	1	Reserved
	7:2	STC_TXD_485 Crossbar
09	0	STC_TX_EN_485 Output Enable
	1	Reserved
	7:2	STC_TX_EN_485 Crossbar
10	0	TXD_232_COM Output Enable
	1	Reserved
	7:2	TXD_232_COM Crossbar
11	0	RTS_232_COM Output Enable
	1	Reserved
	7:2	RTS_232_COM Crossbar
12	0	HD1_TXD Output Enable
	1	HD1_TXD Output Data
	2	HD1_TXD Input Data
	7:3	HD1_TXD Crossbar
13	0	BT_EN Output Enable
	1	BT_EN Output Data
	2	BT_EN Input Data
	7:3	BT_EN Crossbar
14	0	WL_EN Output Enable
	1	WL_EN Data
	7:2	WL_EN Crossbar
15	0:1	Reserved
	2	BT_RTS Input Data
	7:3	Reserved
16	0	BT_CTS Output Enable
	1	BT_CTS Data
	7:2	BT_CTS Crossbar
17	1:0	Reserved
	7:2	BT_RXD Crossbar
18	1:0	Reserved
	7:2	TTYMXC1_RXD Crossbar
19	0	HD1_DIO_1 Output Enable
	1	HD1_DIO_1 Data
	7:2	HD1_DIO_1 Crossbar
20	0	HD1_DIO_2 Output Enable
	1	HD1_DIO_2 Data
	7:2	HD1_DIO_2 Crossbar
21	0	HD1_DIO_3 Output Enable
	1	HD1_DIO_3 Data
	7:2	HD1_DIO_3 Crossbar
22	0	HD1_DIO_4 Output Enable
	1	HD1_DIO_4 Data
	7:2	HD1_DIO_4 Crossbar
23	0	HD1_DIO_5 Output Enable
	1	HD1_DIO_5 Data
	7:2	HD1_DIO_5 Crossbar
24	0	HD1_DIO_6 Output Enable
	1	HD1_DIO_6 Data
	7:2	HD1_DIO_6 Crossbar
25	0	EN_OUT_1 Output Enable
	1	Reserved
	7:2	EN_OUT_1 Crossbar
26	0	EN_OUT_2 Output Enable
	1	Reserved
	7:2	EN_OUT_2 Crossbar
27	0	Reserved
	1	Input Data
	7:2	FPGA_IRQ_1 Crossbar
28	1:0	Reserved
	7:2	STC_TXD_232 Crossbar
29	0	Reserved
	1	push_sw reset
	7:2	Reserved
30	0	Reserved
	1	Reboot (on 1)
	7:2	Reserved
31	0	Reserved
	1	Push SW Input Data
	7:2	Reserved
32	7:0	RS485_CNT0 [23:16]
33	7:0	RS485_CNT0 [15:8]
34	7:0	RS485_CNT0 [7:0]
35	7:0	RS485_CNT1 [23:16]
36	7:0	RS485_CNT1 [15:8]
37	7:0	RS485_CNT1 [7:0]
38	7:0	RS485_CNT2 [23:16]
39	7:0	RS485_CNT2 [15:8]
40	7:0	RS485_CNT2 [7:0]
41	7:0	RS485_CNT3 [23:16]
42	7:0	RS485_CNT3 [15:8]
43	7:0	RS485_CNT3 [7:0]
44	0	TTYMAX0_RXD Output Enable
	1	Reserved
	7:2	TTYMAX0_RXD Crossbar
45	0	TTYMAX1_RXD Output Enable
	1	Reserved
	7:2	TTYMAX1_RXD Crossbar
46	0	TTYMAX2_RXD Output Enable
	1	Reserved
	7:2	TTYMAX2_RXD Crossbar
51	0	R37 Option Resistor (1 = not present)
	1	R36 Option Resistor (1 = not present)
	2	R34 Option Resistor (1 = not present)
	3	R39 Option Resistor (1 = not present)
	7:4	FPGA Revision
53	0	TTYMAX0_CTS Output Enable
	1	Reserved
	7:2	TTYMAX0_CTS Crossbar
54	0	TTYMAX1_CTS Output Enable
	1	Reserved
	7:2	TTYMAX1_CTS Crossbar
55	0	TTYMAX2_CTS Output Enable
	1	Reserved
	7:2	TTYMAX2_CTS Crossbar
56	5:0	HD1_DIO input data
	7:6	DIO2 and DIO 1 input data
57	0	Reserved
	1	CN_99_BOOT_SEL Input Data
	7:2	Reserved
58	0	Reserved
	1	LCD_D10 Input Data
	7:2	Reserved

The FPGA crossbar allows almost any of the FPGA pins to be rerouted on the carrier board. All of the above registers that have a crossbar mux value can be written with these values to change the output value. When using the crossbar pins that are outputs, bit 1 should also be set to allow output enables.

Crossbar Value	Selected Function
0	Do not change
1	BT_RTS
2	BT_TXD
3	TTYMXC4_TXD
4	TTYMXC2_TXD
5	TTYMXC2_CTS
6	TTYMXC1_RTS
7	TTYMXC2_RTS
8	MB_RXD_485
9	STC_RXD_485_3V
10	RXD_232_COM
11	CTS_232_COM
12	STC_RXD
13	HD1_RXD
14	TTYMXC3_TXD
15	TTYMXC1_TXD
16	TTYMAX0_TXD
17	TTYMAX0_TXEN
18	TTYMAX0_RTS
19	TTYMAX1_TXD
20	TTYMAX1_TXEN
21	TTYMAX1_RTS
22	TTYMAX2_TXD
23	TTYMAX2_TXEN
24	TTYMAX2_RTS
25	TTYMXC1_TXEN
26	TTYMXC3_TXEN
27	CLK_12MHZ
28	CLK_14MHZ
29	FPGA_24MHZ_CLK
30	CLK_28MHZ
31	GPIO
32	HD1_DIO_1
33	HD1_DIO_2
34	HD1_DIO_3
35	HD1_DIO_4
36	HD1_DIO_5
37	HD1_DIO_6
38	DIO_1_IN
39	DIO_2_IN
40	LCD_D10