TS-7990 FPGA Sections: Difference between revisions

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| Reserved (Output Only)
| Reserved (Output Only)
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|-
| rowspan=2 | 47
| rowspan=3 | 47
| 7:2
| 7:2
| TXEN3_485 Crossbar
| TXEN3_485 Crossbar
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| rowspan=3 | 53
| rowspan=3 | 53
| 7:2
| 7:2
| TTYMAX0_CTS Crossbar
|-
|-
| 1
| 1
| Reserved
| Reserved
|-
|-
| TTYMAX0_CTS Crossbar
| 0
| 0
| TTYMAX0_CTS Output Enable
| TTYMAX0_CTS Output Enable

Revision as of 18:17, 11 July 2016

The Lattice MachXO2 FPGA provides auto TX enable for RS-485 half duplex, a few more DIO, a crossbar, and it can generate a few preset clocks. Most of these registers are controlled using tshwctl in the ts4900-utils repository. The DIO can be accessed using the sysfs GPIOs 224 to 255 using the "tsgpio" driver. See the #GPIO section for more information on the recommended GPIO access. 

Usage: tshwctl [OPTIONS] ...
Technologic Systems i.mx6 FPGA Utility
     -m, --addr <address>   Sets up the address for a peek/poke
     -v, --poke <value>     Writes the value to the specified address
     -t, --peek             Reads from the specified address
     -i, --mode <8n1>       Used with -a, sets mode like '8n1', '7e2', etc
     -x, --baud <speed>     Used with -a, sets baud rate for auto485
     -a, --autotxen <uart>  Enables autotxen for supported CPU UARTs
                              Uses baud/mode if set or reads the current
                              configuration of that uart
     -c, --dump             Prints out the crossbar configuration
     -g, --get              Print crossbar for use in eval
     -s, --set              Read environment for crossbar changes
     -q, --showall          Print all possible FPGA inputs and outputs.
     -h, --help             This message

The GPIO registers below include a crossbar, output enable, and data bit. The crossbar picks between GPIO (with crossbar value 31), and all other modes described in the next table. While the crossbar is set to GPIO, bit 0 is used as an output enable. When bit 0 is set to 0, bit 1 reflects the input value. When bit 0 is set to 1, bit 1 reflects the value that will be output.

Addr Bits Function
00 7:2 TTYMXC2_RXD Crossbar
1 TTYMXC2_RXD Output Data
0 Reserved (Output only)
01 7:2 TTYMXC4_RXD Crossbar
1 TTYMXC4_RXD Output Data
0 Reserved (Output only)
02 7:2 TTYMXC2_CTS Crossbar
1 TTYMXC2_CTS Data
0 TTYMXC2_CTS Output Enable
03 7:2 TTYMXC3_RXD Crossbar
1 TTYMXC3_RXD Output Data
0 Reserved (Output Only)
04 7:2 TTYMXC1_CTS Crossbar
1 TTYMXC1_CTS Output Data
0 Reserved (Output Only)
05 7:2 TTYMXC2_RTS Crossbar
1 TTYMXC2_RTS Data
0 TTYMXC2_RTS Output Enable
06 7:2 DIO_8 Crossbar
1 DIO_8 Data
0 DIO_8 Output Enable
07 7:2 DIO_9 Crossbar
1 DIO_9 Data
0 DIO_9 Output Enable
08 7:2 TXD1_485 Crossbar
1 TXD1_485 Output Data
0 Reserved (Output Only)
09 7:2 TXD2_485 Crossbar
1 TXD2_485 Output Data
0 Reserved (Output Only)
10 7:2 TXD3_485 Crossbar
1 TXD3_485 Output Data
0 Reserved (Output Only)
11 7:2 TXEN1_485 Crossbar
1 TXEN1_485 Output Data
0 Reserved (Output Only)
12 7:2 TXEN2_485 Crossbar
1 TXEN2_485 Output Data
0 Reserved (Output Only)
13 7:2 Reserved
1 BT_EN Output data
0 Reserved
14 7:2 Reserved
1 WL_EN Output data
0 Reserved
16 7:2 BT_CTS Crossbar
1 BT_CTS Data
0 BT_CTS Output Enable
17 7:2 BT_RXD Crossbar
1 BT_RXD Output Data
0 Reserved (Output Only)
18 7:2 TTYMXC1_RXD Crossbar
1 Reserved
0 Reserved (Output Only)
19 7:2 DIO_0 Crossbar
1 DIO_0 Data
0 DIO_0 Output Enable
20 7:2 DIO_1 Crossbar
1 DIO_1 Data
0 DIO_1 Output Enable
21 7:2 DIO_2 Crossbar
1 DIO_2 Data
0 DIO_2 Output Enable
22 7:2 DIO_3 Crossbar
1 DIO_3 Data
0 DIO_3 Output Enable
23 7:2 DIO_4 Crossbar
1 DIO_4 Data
0 DIO_4 Output Enable
24 7:2 DIO_5 Crossbar
1 DIO_5 Data
0 DIO_5 Output Enable
25 7:2 DIO_6 Crossbar
1 DIO_6 Data
0 DIO_6 Output Enable
26 7:2 DIO_7 Crossbar
1 DIO_7 Data
0 DIO_7 Output Enable
27 7:2 FPGA_IRQ_1 Crossbar Value
1 FGPA_IRQ_1 Output Data
0 Reserved (Output Only)
28 7:0 Reserved
29 7:0 Reserved
30 7:2 Reserved
1 Reboot (on 1) [1]
0 Reserved
31 7:0 Reserved
32 7:0 RS485_CNT0 [23:16]
33 7:0 RS485_CNT0 [15:8]
34 7:0 RS485_CNT0 [7:0]
35 7:0 RS485_CNT1 [23:16]
36 7:0 RS485_CNT1 [15:8]
37 7:0 RS485_CNT1 [7:0]
38 7:0 RS485_CNT2 [23:16]
39 7:0 RS485_CNT2 [15:8]
40 7:0 RS485_CNT2 [7:0]
41 7:0 RS485_CNT3 [23:16]
42 7:0 RS485_CNT3 [15:8]
43 7:0 RS485_CNT3 [7:0]
44 7:2 TTYMAX0_RXD Crossbar (Output Only)
1 TTYMAX0_RXD Output Data
0 Reserved (Output Only)
45 7:2 TTYMAX1_RXD Crossbar
1 TTYMAX1_RXD Output Data
0 Reserved (Output Only)
46 7:2 TTYMAX2_RXD Crossbar
1 TTYMAX2_RXD Output Data
0 Reserved (Output Only)
47 7:2 TXEN3_485 Crossbar
1 TXEN3_485 Output Data
0 Reserved (Output Only)
51 7:4 FPGA Revision
3 R152 Input Value
2 R34 Input Value
1 R36 Input Value
0 R37 Input Value
53 7:2 TTYMAX0_CTS Crossbar
1 Reserved
0 TTYMAX0_CTS Output Enable
54 7:2 TTYMAX1_CTS Crossbar
1 Reserved
0 TTYMAX1_CTS Output Enable
55 7:2 TTYMAX2_CTS Crossbar
1 Reserved
0 TTYMAX2_CTS Output Enable
56 7:0 DIO 7:0 Input Data
57 7:4 Reserved
3 OKAYA_PRESENT
2:1 DIO 9:8 Input Data
0 CN99_BOOT_SEL_PAD [2]
58 7:0 Reserved
59 7:1 Reserved
0 TOUCH_RESET Output Data
60 7:2 Reserved
1 MT_LCD_PRESENT
0 Reserved
61 7:2 Reserved
1 EN_SPKR Output Data
0 Reserved
  1. ↑ This power cycles all rails
  2. ↑ This is used to select the offboard SPI primarily just used for production purposes.

FPGA Crossbar

The FPGA crossbar allows almost any of the FPGA pins to be rerouted. All of the FPGA registers that have a crossbar mux value can be written with these values to change the output value. When using the crossbar pins that are outputs, bit 1 should also be set to allow output enables.

Crossbar Value Selected Function
0 Do not change
1 BT_RTS
2 BT_TXD
3 TTYMXC4_TXD
4 TTYMXC2_TXD
5 TTYMXC2_CTS
6 TTYMXC1_RTS
7 TTYMXC2_RTS
8 MB_RXD_485
9 STC_RXD_485_3V
10 RXD_232_COM
11 CTS_232_COM
12 STC_RXD
13 HD1_RXD
14 TTYMXC3_TXD
15 TTYMXC1_TXD
16 TTYMAX0_TXD
17 TTYMAX0_TXEN
18 TTYMAX0_RTS
19 TTYMAX1_TXD
20 TTYMAX1_TXEN
21 TTYMAX1_RTS
22 TTYMAX2_TXD
23 TTYMAX2_TXEN
24 TTYMAX2_RTS
25 TTYMXC1_TXEN
26 TTYMXC3_TXEN
27 CLK_12MHZ
28 CLK_14MHZ
29 FPGA_24MHZ_CLK
30 CLK_28MHZ
31 GPIO


For example, we can remap three ttyMAX ports to the HD1 GPIO.

Pin Function
HD1_DIO_1 ttyMAX0 txd
HD1_DIO_2 ttyMAX0 rxd
HD1_DIO_3 ttyMAX1 txd
HD1_DIO_4 ttyMAX1 rxd
HD1_DIO_5 ttyMAX2 txd
HD1_DIO_6 ttyMAX2 rxd 
tshwctl --dump

This will return the mapping of all of the pins as they are currently set. These are the relevant pins: 

     FPGA Pad (DIR) (VAL) FPGA Output
       MB_TXD ( in) (  0) TTYMAX1_TXD
  STC_TXD_485 ( in) (  0) TTYMAX0_TXD
  RTS_232_COM ( in) (  0) TTYMAX2_TXD
    HD1_DIO_1 ( in) (  0) GPIO
    HD1_DIO_2 ( in) (  0) GPIO
    HD1_DIO_3 ( in) (  0) GPIO
    HD1_DIO_4 ( in) (  0) GPIO
    HD1_DIO_5 ( in) (  0) GPIO
    HD1_DIO_6 ( in) (  0) GPIO
  TTYMAX0_RXD ( in) (  0) STC_RXD_485_3V
  TTYMAX1_RXD ( in) (  0) MB_RXD_485
  TTYMAX2_RXD ( in) (  0) CTS_232_COM

...

The tshwctl tool uses the bash environment to set/get pin status. To remap these pins: 

eval $(tshwctl --get)
export HD1_DIO_1=TTYMAX0_TXD
export HD1_DIO_3=TTYMAX1_TXD
export HD1_DIO_5=TTYMAX2_TXD
export TTYMAX0_RXD=HD1_DIO_2
export TTYMAX1_RXD=HD1_DIO_4
export TTYMAX2_RXD=HD1_DIO_6

# These last 3 aren't required, but this will disable ttyMAX pins on
# their default locations.  Without this, writes to /dev/ttyMAX0 
# would go to both STC_TXD_485 and to HD1_DIO_1.
export MB_TXD=GPIO
export STC_TXD_485=GPIO
export RTS_232_COM=GPIO

# This will read the environment and look for the PAD names 
# for any changes and apply them.
tshwctl --set

# The TTY_MAX*_TXD lines will only output data
# if they pins are outputs, so set these pins 
echo 243 > /sys/class/gpio/export # HD1_DIO_1
echo high > /sys/class/gpio/gpio243/direction
echo 245 > /sys/class/gpio/export # HD1_DIO_3
echo high > /sys/class/gpio/gpio245/direction
echo 247 > /sys/class/gpio/export # HD1_DIO_5
echo high > /sys/class/gpio/gpio247/direction
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