TS-8390-47xx ADC Header: Difference between revisions

From embeddedTS Manuals
(Created page with "The Analog to Digital Converter consists of a 4-channel 16 bit sigma-delta converter and two, 2-channel analog switches. These are configured to allow input and conversion on...")
 
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Our default core shipped with the TS-4710 does not include support for ADC.  Support can be included with this [https://files.embeddedTS.com/ts-socket-macrocontrollers/ts-4710-linux/binaries/ts-bitstreams/ts4710-fpga-rev3-default-ADC.vme.bz2 opencore bitstream].  See the [[#FPGA|FPGA]] section for more information on loading this bitstream, or building a custom one.
This example prints out all 6 ADC readings in millivolts:
<source lang=c>
#include <stdio.h>
#include <stdint.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <assert.h>
#include <fcntl.h>
volatile uint16_t *syscon = 0;
inline void syscon_init() {
if(syscon == 0) {
int mem = open("/dev/mem", O_RDWR|O_SYNC);
syscon = mmap(0,
getpagesize(),
PROT_READ|PROT_WRITE,
MAP_SHARED,
mem,
0x80004000);
}
}
uint16_t peek16(uint16_t addr)
{
syscon_init();
return syscon[addr/2];
}
void poke16(uint16_t addr, uint16_t value)
{
syscon_init();
syscon[addr/2] = value;
}
int main()
{
int x, i;
// Select AN_SEL line:
// For the TS-TPC-8390 baseboard:
poke16(0x400, 0x28);
// enable all 6 channels
poke16(0x402, 0x3f);
// allow time for conversions
usleep(500000);
for (i = 1; i <= 6; i++) {
x = (signed short)peek16(0x402 + 2*i);
                if (i > 2) x = (x * 1006)/200;
                x = (x * 2048)/0x8000;
                printf("adc%d=%d\n", i, x);
}
return 0;
}
</source>
Running this code on the TS-TPC-8390 with pin 7 of the ADC header (channel 3) connected to 3.3V returns:
  root@ts4700:~# ./adctest
  adc1=0
  adc2=0
  adc3=3302
  adc4=0
  adc5=0
  adc6=0
{| class=wikitable
|+ ADC Core Register Map
|-
! Offset
! Bits
! Description
|-
| rowspan=5 | 0x0
| 15:8
| Core ID register (reads 0xad)
|-
| 7:6
| Reserved
|-
| 5:4
|
{| class=wikitable
|+ Analog Select Pin
|-
! Value
! Description
|-
| 0
| Do not use an AN+SEL
|-
| 1
| use CN1 pin 77 for AN_SEL (TS-8100)
|-
| 2
| use CN1 pin 74 for AN_SEL (TS-8390)
|-
| 3
| Reserved
|}
|-
| 3:2
|
{| class=wikitable
|+ Speed
|-
! Value
! Description
|-
| 0
| 240Hz, 12 bit resolution
|-
| 1
| 60Hz, 14 bit resolution
|-
| 2
| 15Hz, 16 bit resolution
|-
| 3
| Reserved
|}
|-
| 1:0
|
{| class=wikitable
|+ Programmable Gain Amplifier
|-
! Value
! Description
|-
| 0
| No gain
|-
| 1
| 2x gain
|-
| 2
| 4x gain
|-
| 3
| 8x gain
|}
|-
| 0x2
| 15:0
| Channel Mask
|-
| 0x4
| 15:0
| Channel 1 most recent conversion value
|-
| 0x6
| 15:0
| Channel 2 most recent conversion value
|-
| 0x8
| 15:0
| Channel 3 most recent conversion value
|-
| 0xa
| 15:0
| Channel 4 most recent conversion value
|-
| 0xc
| 15:0
| Channel 5 most recent conversion value
|-
| 0xe
| 15:0
| Channel 6 most recent conversion value
|}
The channel mask register controls which channels are enabled.  Bits 0-5 enable channels 1-6 respectively.  If a given channel is not enabled, (enable bit == 0) it will not be sampled and its conversion value register will contain an obsolete and meaningless value.  The more channels that are enabled, the lower the sampling speed on each channel.

Latest revision as of 17:31, 17 January 2022

The Analog to Digital Converter consists of a 4-channel 16 bit sigma-delta converter and two, 2-channel analog switches. These are configured to allow input and conversion on two differential channels and 4 single ended channels. The 6-channel Analog to Digital signals are contained on connector HD5 which is a 16 pin (2x8) 0.1" spacing header. The connector layout and the signals carried by each pin are defined below. The input range for the differential input channels is 0- 2 VDC, and the input range on the single-ended channel is nominally 0-10 VDC.

Pinout Header
Pin Type Signal
1 Single ended Channel 6
2 N/A GND
3 Single ended Channel 5
4 N/A GND
5 Single ended Channel 4
6 N/A GND
7 Single ended Channel 3
8 N/A GND
9 N/A Not connected
10 N/A GND
11 Differential Channel 2-
12 Differential Channel 2+
13 N/A GND
14 Differential Channel 1-
15 Differential Channel 1+
16 N/A GND
TS-8390-ADC.png

Our default core shipped with the TS-4710 does not include support for ADC. Support can be included with this opencore bitstream. See the FPGA section for more information on loading this bitstream, or building a custom one.

This example prints out all 6 ADC readings in millivolts: 

#include <stdio.h>
#include <stdint.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <assert.h>
#include <fcntl.h>


volatile uint16_t *syscon = 0;
inline void syscon_init() {
	if(syscon == 0) {
		int mem = open("/dev/mem", O_RDWR|O_SYNC);
		syscon = mmap(0,
			getpagesize(),
			PROT_READ|PROT_WRITE,
			MAP_SHARED,
			mem,
			0x80004000);
	}
}

uint16_t peek16(uint16_t addr)
{
	syscon_init();
	return syscon[addr/2];
}

void poke16(uint16_t addr, uint16_t value)
{
	syscon_init();
	syscon[addr/2] = value;
}

int main()
{
	int x, i;

	// Select AN_SEL line:
	// For the TS-TPC-8390 baseboard:
	poke16(0x400, 0x28);

	// enable all 6 channels
	poke16(0x402, 0x3f);

	// allow time for conversions
	usleep(500000);

	for (i = 1; i <= 6; i++) {
		x = (signed short)peek16(0x402 + 2*i);
                if (i > 2) x = (x * 1006)/200;
                x = (x * 2048)/0x8000;
                printf("adc%d=%d\n", i, x);
	}

	return 0;
}


Running this code on the TS-TPC-8390 with pin 7 of the ADC header (channel 3) connected to 3.3V returns: 

 root@ts4700:~# ./adctest 
 adc1=0
 adc2=0
 adc3=3302
 adc4=0
 adc5=0
 adc6=0
ADC Core Register Map
Offset Bits Description
0x0 15:8 Core ID register (reads 0xad)
7:6 Reserved
5:4
Analog Select Pin
Value Description
0 Do not use an AN+SEL
1 use CN1 pin 77 for AN_SEL (TS-8100)
2 use CN1 pin 74 for AN_SEL (TS-8390)
3 Reserved
3:2
Speed
Value Description
0 240Hz, 12 bit resolution
1 60Hz, 14 bit resolution
2 15Hz, 16 bit resolution
3 Reserved
1:0
Programmable Gain Amplifier
Value Description
0 No gain
1 2x gain
2 4x gain
3 8x gain
0x2 15:0 Channel Mask
0x4 15:0 Channel 1 most recent conversion value
0x6 15:0 Channel 2 most recent conversion value
0x8 15:0 Channel 3 most recent conversion value
0xa 15:0 Channel 4 most recent conversion value
0xc 15:0 Channel 5 most recent conversion value
0xe 15:0 Channel 6 most recent conversion value

The channel mask register controls which channels are enabled. Bits 0-5 enable channels 1-6 respectively. If a given channel is not enabled, (enable bit == 0) it will not be sampled and its conversion value register will contain an obsolete and meaningless value. The more channels that are enabled, the lower the sampling speed on each channel.

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