TS-8390-47xx DIO Header: Difference between revisions
From embeddedTS Manuals
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Latest revision as of 13:19, 11 September 2013
The DIO header is a 0.1" pitch 2x40 header.
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- ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are only intended for production. Use of these for reprogramming the FPGA is not recommended or supported. See the #FPGA Programming section for more information about the supported mechanism for reloading the FPGA.
- ↑ Pull low to reset the CPU. Do not drive high (use open drain).