TS-8390-47xx DIO Header
From embeddedTS Manuals
The DIO header is a 0.1" pitch 2x40 header.
Pin | Description |
1 | FPGA TDO [1] |
2 | FPGA TMS [1] |
3 | Ground |
4 | FPGA TDI [1] |
5 | RS232 XUART 5 RXD |
6 | FPGA TCk [1] |
7 | TTL DEBUG_TXD |
8 | TTL DEBUG_RXD |
9 | SPI_MISO |
10 | 3.3V Supply |
11 | SPI_CS2# |
12 | BUF_SPI_MOSI |
13 | BUF_SPI_CS1# |
14 | BUF_SPI_CLK# |
15 | 5V Supply |
16 | EXT_RESET# [2] |
17 | MFP_48 |
18 | Ground |
19 | DIO_28 |
20 | DIO_26 |
21 | DIO_08 |
22 | DIO_24 |
23 | DIO_09 |
24 | DIO_23 |
25 | DIO_22 |
26 | DIO_02 |
27 | DIO_03 |
28 | DIO_01 |
29 | DIO_04 |
30 | DIO_00 |
31 | MFP_37 |
32 | MFP_45 |
33 | MFP_54 |
34 | MFP_42 |
35 | DIO_27 |
36 | MFP_44 |
37 | I2C_DAT |
38 | MFP_39 |
39 | I2C_CLK |
40 | MFP_46 |
|- |
[[File:TS-8390-DIO.png|400px |
- ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are only intended for production. Use of these for reprogramming the FPGA is not recommended or supported. See the #FPGA Programming section for more information about the supported mechanism for reloading the FPGA.
- ↑ Pull low to reset the CPU. Do not drive high (use open drain).