TS-8820-4720: Difference between revisions
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NOTICE: This article is a work in progress. If you have questions about using the TS-8820-4720, please call our support team, or email support@embeddedarm.com. Thanks! | |||
= Overview = | = Overview = | ||
The TS-8820-4720 is an industrial Building Controller that knows how to Linux. | The TS-8820-4720 is an industrial Building Controller that knows how to Linux. | ||
Revision as of 15:42, 11 August 2016
NOTICE: This article is a work in progress. If you have questions about using the TS-8820-4720, please call our support team, or email support@embeddedarm.com. Thanks!
Overview
The TS-8820-4720 is an industrial Building Controller that knows how to Linux.
Getting Started
The Getting Started section will go here.
Features
Enumerated list of device functions here.
External Interfaces
Everything with a connector. Describe them all here.
TS-8820 Register Map
This register map assumes a base address offset. The offset when using the TS-4720 is 0x80008000. This address must first be activated using the MUXBUS enable and timing registers on the CPU module. On the TS-4720, write 0xF3FF to the address 0x80004004. Sample code for accessing the functions described in this table are largely encompassed by the ts8820ctl software available on the TS FTP Site.
| Offset | Bits | Description |
|---|---|---|
| 0x0 | 15:0 | Model ID: Reads 0x8820 |
| 0x2 | 15:11 | Reserved |
| 10 | Pull-up 5-8 enable | |
| 9 | Pull-up 3-4 enable | |
| 8 | Pull-up 1-2 enable | |
| 7 | H-bridge 2 enable (contacts go high-Z otherwise) | |
| 6 | H-bridge 1 enable (contacts go high-Z otherwise) | |
| 5 | H-bridge 2 direction | |
| 4 | H-bridge 1 direction | |
| 3:0 | FPGA Revision | |
| 0x4 | 15:14 | Reserved |
| 13:0 | Digital inputs 14:1 | |
| 0x6 | 15:10 | Reserved |
| 9:0 | SRAM Page register | |
| 0x8 | 15:12 | Reserved |
| 11:6 | Override Digital Outputs 6:1 with PWM | |
| 5:0 | Digital Output Values 6:1 | |
| 0xa | 15:0 | Reserved |
| 0xc | 15:0 | Reserved |
| 0xe | 15:0 | Reserved |
| 0x10 | 15:13 | PWM #1 Prescaler |
| 12:0 | PWM #1 Duty Cycle | |
| 0x12 | 15:13 | PWM #2 Prescalar |
| 12:0 | PWM #2 Duty Cycle | |
| 0x14 | 15:13 | PWM #3 Prescaler |
| 12:0 | PWM #3 Duty Cycle | |
| 0x16 | 15:13 | PWM #4 Prescaler |
| 12:0 | PWM #4 Duty Cycle | |
| 0x18 | 15:13 | PWM #5 Prescaler |
| 12:0 | PWM #5 Duty Cycle | |
| 0x1a | 15:13 | PWM #6 Prescaler |
| 12:0 | PWM #6 Duty Cycle | |
| 0x1c | 15:13 | PWM #7 Prescaler |
| 12:0 | PWM #7 Duty Cycle | |
| 0x1e | 15:13 | PWM #8 Prescaler |
| 12:0 | PWM #8 Duty Cycle | |
| 0x20 | 15:0 | Pulse Counter #1 (RO) |
| 0x22 | 15:0 | Pulse Counter #2 (RO) |
| 0x24 | 15:0 | Pulse Counter #3 (RO) |
| 0x26 | 15:0 | Pulse Counter #4 (RO) |
| 0x28 | 15:0 | Pulse Counter #5 (RO) |
| 0x2a | 15:0 | Pulse Counter #6 (RO) |
| 0x2c | 15:0 | Pulse Counter #7 (RO) |
| 0x2e | 15:0 | Pulse Counter #8 (RO) |
| 0x30 | 15:0 | Pulse Counter #9 (RO) |
| 0x32 | 15:0 | Pulse Counter #10 (RO) |
| 0x34 | 15:0 | Pulse Counter #11 (RO) |
| 0x36 | 15:0 | Pulse Counter #12 (RO) |
| 0x38 | 15:0 | Pulse Counter #13 (RO) |
| 0x3a | 15:0 | Pulse Counter #14 (RO) |
| 0x3c | 15:0 | Reserved |
| 0x3e | 15:0 | Reserved |
| 0x80 | 15:0 | ADC Core ID (reads 0xadc1) |
| 0x82 | 15:8 | ADC Channel Mask (0 = do not save channel data) |
| 7:6 | Highest number chip to use (0-3, if 01 then sample chip 0 and chip 1) | |
| 5 | 1 = Force standby | |
| 4 | 1 = Use standby between samples to save power | |
| 3 | 1 = Smart DMA IRQ mode | |
| 2 | 1 = Enable IRQ | |
| 1 | 1 = Collect samples, 0 = stop | |
| 0 | 1 = Reset ADC chips and all FIFOs | |
| 0x84 | 15 | 1 = There has been a FIFO overflow since last reset |
| 14:0 | Number of samples available to be read | |
| 0x86 | 15:0 | Sample Data (RO) |
| 0x88 | 15:0 | Sampling period LSB (RW) |
| 0x8a | 15:0 | Sampling period MSB (RW) |
| 0x8c | 15:0 | IRQ Threshold (RW) |
| 0x8e | 15:0 | DMA transfer size for smart mode (RW) (TODO) |
| 0x90 | 15:0 | Reserved |
| 0x92 | 15:0 | Reserved |
| 0x94 | 15:0 | Reserved |
| 0x96 | 15:0 | Reserved |
| 0x98 | 15:0 | Reserved |
| 0x9a | 15:0 | Reserved |
| 0x9c | 15:0 | Reserved |
| 0x9e | 15:0 | Reserved |
| 0xa0 | 15:0 | DAC 1 Control Register |
| 0xa2 | 15:0 | DAC 2 Control Register |
| 0xa4 | 15:0 | DAC 3 Control Register |
| 0xa6 | 15:0 | DAC 4 Control Register |
Product Notes
Some parts may cause cancer in the State of California.