NOTICE: This article is a work in progress. If you have questions about using the TS-8820-4720, please call our support team, or email support@embeddedarm.com. Thanks!
Overview
The TS-8820-4720 is an industrial Building Controller that knows how to Linux.
Getting Started
The Getting Started section will go here.
Features
Enumerated list of device functions here.
External Interfaces
Terminal Blocks
Note:
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If you have a REV A board disregard the P1-P10 labeling as printed on the PCB.
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P9
Pin
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Description
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1
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DAC 3
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2
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Ground
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3
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DAC 4
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4
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Ground
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5
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Spare 1
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6
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Spare 2
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7
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Spare 3
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8
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Spare 4
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9
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Spare 5
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10
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Spare 6
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11
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Spare 7
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12
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Spare 8
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P10
Pin
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Description
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1
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Not Connected
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2
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Not Connected
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3
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ISO Common
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4
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ISO Common
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5
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XUART0 ISO RS485+
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6
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XUART0 ISO RS485-
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7
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XUART1 ISO RS232 TXD
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8
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XUART1 ISO RS232 RXD
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9
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Not Connected
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10
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CAN Common
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11
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CAN_H
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12
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CAN_L
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Ethernet Connector
The TS-8820 can connect to any Ethernet LAN. Ethernet is fully supported by any TS-SOCKET macrocontroller. The Ethernet connector includes LEDs indicating link and activity. The link LED should be on whenever the TS-8820 is powered and connected to a LAN. This connector allows the TS-8820 to be powered by PoE.
USB Host
The USB is available on two ports as a USB 2.0 host.
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Header PIN
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Name
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1
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USB_5V
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2
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HOSTA_USB_M
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3
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HOSTA_USB_P
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4
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GND
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DB9 Connector
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Pin
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Description
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1
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XUART4 RS485+
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2
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Debug Console RS232 RXD
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3
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Debug Console RS232 TXD
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4
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Not Connected
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5
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Ground
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6
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XUART4 RS485-
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7
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XUART2 RS232 TXD
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8
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XUART2 RS232 RXD
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9
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Not Connected
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TS-8820 Register Map
This register map assumes a base address offset. The offset when using the TS-4720 is 0x80008000. This address must first be activated using the MUXBUS enable and timing registers on the CPU module. On the TS-4720, write 0xF3FF to the address 0x80004004. Sample code for accessing the functions described in this table are largely encompassed by the ts8820ctl software available on the TS FTP Site.
Offset
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Bits
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Description
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0x0
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15:0
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Model ID: Reads 0x8820
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0x2
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15:11
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Reserved
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10
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Pull-up 5-8 enable
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9
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Pull-up 3-4 enable
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8
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Pull-up 1-2 enable
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7
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H-bridge 2 enable (contacts go high-Z otherwise)
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6
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H-bridge 1 enable (contacts go high-Z otherwise)
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5
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H-bridge 2 direction
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4
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H-bridge 1 direction
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3:0
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FPGA Revision
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0x4
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15:14
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Reserved
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13:0
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Digital inputs 14:1
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0x6
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15:10
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Reserved
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9:0
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SRAM Page register
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0x8
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15:12
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Reserved
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11:6
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Override Digital Outputs 6:1 with PWM
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5:0
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Digital Output Values 6:1
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0xa
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15:0
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Reserved
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0xc
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15:0
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Reserved
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0xe
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15:0
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Reserved
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0x10
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15:13
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PWM #1 Prescaler
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12:0
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PWM #1 Duty Cycle
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0x12
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15:13
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PWM #2 Prescalar
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12:0
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PWM #2 Duty Cycle
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0x14
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15:13
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PWM #3 Prescaler
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12:0
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PWM #3 Duty Cycle
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0x16
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15:13
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PWM #4 Prescaler
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12:0
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PWM #4 Duty Cycle
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0x18
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15:13
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PWM #5 Prescaler
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12:0
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PWM #5 Duty Cycle
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0x1a
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15:13
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PWM #6 Prescaler
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12:0
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PWM #6 Duty Cycle
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0x1c
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15:13
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PWM #7 Prescaler
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12:0
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PWM #7 Duty Cycle
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0x1e
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15:13
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PWM #8 Prescaler
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12:0
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PWM #8 Duty Cycle
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0x20
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15:0
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Pulse Counter #1 (RO)
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0x22
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15:0
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Pulse Counter #2 (RO)
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0x24
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15:0
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Pulse Counter #3 (RO)
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0x26
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15:0
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Pulse Counter #4 (RO)
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0x28
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15:0
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Pulse Counter #5 (RO)
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0x2a
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15:0
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Pulse Counter #6 (RO)
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0x2c
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15:0
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Pulse Counter #7 (RO)
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0x2e
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15:0
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Pulse Counter #8 (RO)
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0x30
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15:0
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Pulse Counter #9 (RO)
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0x32
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15:0
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Pulse Counter #10 (RO)
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0x34
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15:0
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Pulse Counter #11 (RO)
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0x36
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15:0
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Pulse Counter #12 (RO)
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0x38
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15:0
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Pulse Counter #13 (RO)
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0x3a
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15:0
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Pulse Counter #14 (RO)
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0x3c
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15:0
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Reserved
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0x3e
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15:0
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Reserved
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0x80
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15:0
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ADC Core ID (reads 0xadc1)
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0x82
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15:8
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ADC Channel Mask (0 = do not save channel data)
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7:6
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Highest number chip to use (0-3, if 01 then sample chip 0 and chip 1)
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5
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1 = Force standby
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4
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1 = Use standby between samples to save power
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3
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1 = Smart DMA IRQ mode
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2
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1 = Enable IRQ
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1
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1 = Collect samples, 0 = stop
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0
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1 = Reset ADC chips and all FIFOs
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0x84
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15
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1 = There has been a FIFO overflow since last reset
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14:0
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Number of samples available to be read
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0x86
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15:0
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Sample Data (RO)
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0x88
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15:0
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Sampling period LSB (RW)
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0x8a
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15:0
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Sampling period MSB (RW)
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0x8c
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15:0
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IRQ Threshold (RW)
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0x8e
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15:0
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DMA transfer size for smart mode (RW) (TODO)
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0x90
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15:0
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Reserved
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0x92
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15:0
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Reserved
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0x94
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15:0
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Reserved
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0x96
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15:0
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Reserved
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0x98
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15:0
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Reserved
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0x9a
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15:0
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Reserved
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0x9c
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15:0
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Reserved
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0x9e
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15:0
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Reserved
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0xa0
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15:0
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DAC 1 Control Register
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0xa2
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15:0
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DAC 2 Control Register
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0xa4
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15:0
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DAC 3 Control Register
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0xa6
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15:0
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DAC 4 Control Register
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Product Notes
Some parts may cause cancer in the State of California.