TS-8820-4800
 | |
| Product Page | |
| Image Gallery | |
| Software Support | |
|---|---|
| TS-8820 source directory |
Overview
The TS-8820-BOX is a rugged, feature-rich TS-SOCKET based baseboard and Macrocontroller combination for industrial applications. Powered by either the TS-4700 or TS-4800 Macrocontroller Computer on Module, the TS-8820-BOX provides a variety of electrically isolated I/O.. The TS-8820-BOX enclosure exposes the I/O on rugged screw terminals while protecting the macrocontroller and other sensitive electronics. The TS-8820-BOX with an 800MHz TS-4700 or TS-4800 in the aluminum enclosure provides a tough, durable, flexible, powerful, and affordable industrial process control system platform.
TS-4800
See the TS-4800 page for functionality regarding the CPU, FPGA, and OS.
|
Freescale i.MX515 800MHz Cortex-A8 |
Getting Started
- Place the TS-8820 base board on a firm non-conductive surface.
- Carefully, insert the TS-4000 Series Macrocontroller by aligning and pressing evenly and firmly onto the pair of mating connectors
- Connect the console serial terminal cable
- Connect the Ethernet cable if applicable.
- Connect the GND and POWER screw terminals to a voltage source from 10V to 30V DC.
- Alternatively, the board can be powered through POE
- Apply power
- Monitor the TS-SOCKET SBC using a terminal emulator connected to the serial console port to verify that the board is operating properly
See the TS-4800 page for more details on dealing with the functionality of the macrocontroller.
Features
FPGA
The TS-8820 is powered by a Lattice XP2 FPGA with 5000 LUTs. Many but not all of the features listed in chapter 5 are driven by FPGA logic. The hardware functionality described in this document is programmed in the FPGA at the factory by default. The TS-SOCKET macrocontroller also has an FPGA, but when an FPGA is mentioned in this document it should be assumed that the TS-8820 FPGA is being discussed.
The macrocontroller CoM communicates with the TS-8820 FPGA using the MUXBUS, a simple address/data bus defined by Technologic Systems and implemented in the macrocontroller FPGA. TS-8820 application developers do not need to understand the full hardware stack that enables TS-8820 registers to be accessed in memory space. It is necessary to program the MUXBUS registers with values that work for the TS-8820. The TS-8820 FPGA can handle very aggressive MUXBUS timing. See ts8820ctl source code for an example.
For applications that require custom logic or interfaces, contact Technologic Systems regarding FPGA customization.
Non-Volatile RAM
The TS-8820 provides 2MB of battery backed static RAM. The RAM is accessed through a 4KB memory window. After programming the SRAM page register, 16 bit reads or writes can be performed to any part of the page.
This can be accessed through ts8820ctl:
echo "test" | ts8820ctl -W 5
ts8820ctl -R 5
| Note: | The SRAM is not populated by default. See U16 to verify the presence on your board. If you require battery backed SRAM please contact us. |
Battery Socket
The coin cell battery is not required for TS-8820 operation. The battery provides backup power for the static RAM and for the real time clock (on the macrocontroller). Without a battery, a loss of power will result in a loss of RTC time and SRAM data.
Digital Outputs
The outputs are controlled through ts8820ctl. To set the outputs, you would set the LSB of a 16 bit value passed to ts8820ctl. For example, to toggle OUT5:
ts8820ctl --setdio=0x10
Isolated Outputs
The 4 isolated outputs each have a positive and negative terminal. Each output acts as a passive switch, allowing current to flow only when it is activated. Isolated output terminals are on P3.
Non-Isolated Outputs
Outputs 5 and 6 are non-isolated and appear on P9. When set low, they can sink 1000mA.
PWM
PWMs 1 to 6 feed digital outputs 1 to 6, respectively, only if the PWM override bit is set for the output in question. PWMs 7 and 8 are used for H-bridges. If an H-bridge is not enabled, both contacts will be high impedance. If it is enabled, it will have one side tied to ground and the other side driven by the PWM. The direction bit can be toggled at any time to toggle the H-bridge direction. "Brake mode" with both sides high is not supported by the current FPGA version.
For all 8 PWMs, the PWM frequency is approximately 12207/(2^prescalar). PWM duty cycle has 12 bits of resolution. If bit 13 is set, the output will be 100% high. Otherwise, the duty cycle setting is divided by 4096 to give the effective duty cycle.
To control this using ts8820ctl:
# --prescalar= sets the frequency to (12207/(2^VALUE))Hz.
# --mvolts= sets the duty cycle from 0-10000
# --pwm= sets which channels have PWM active
ts8820ctl --pwm=5 --mvolts=5000 --prescalar=20
Digital Inputs
The digital inputs can be read using ts8820ctl. The command:
ts8820ctl --getdio
The LSB of the returned 16 bit number will correspond with the digital inputs.
Buffered Inputs
Digital inputs 9 to 14 are buffered but not isolated. They have a nominal threshold of 2.5V and a 3.24K pull-up to 5V. These inputs are 40V tolerant. They are on terminal block P9.
Isolated Inputs
Each isolated input has a positive and negative terminal. In order to activate the input, a potential of at least 3V and not more than 30V must be generated across these terminals. Isolated input terminals are on P1 and P3.
ADC Channels
The 16 ADC channels are on P4, P6, and P5. Inputs for these channels must be in the -10V to +10V range. It is also possible to select a -5V to +5V range in software. On P4, P6, and P5, all even numbered terminals are connected to ground. Odd numbered terminals are used for ADC inputs and DAC outputs.
To sample the ADC channels:
# This will sample the ADC inputs 5 times a second.
ts8820ctl --sample=5
This will sample for 1 second 5 times. For example, this would return:
Collected 80 samples total. Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Ch 9 Ch10 Ch11 Ch12 Ch13 Ch14 Ch15 Ch16 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 9999 9999 9999 9999 9999 9999 9999 9999 2143 2136 2141 2144 2148 2143 2142 2143 9999 9999 9999 9999 9999 9999 9999 9999 2142 2137 2141 2144 2147 2143 2142 2142 9999 9999 9999 9999 9999 9999 9999 9999 2142 2136 2140 2144 2147 2143 2142 2142 9999 9999 9999 9999 9999 9999 9999 9999 2142 2136 2141 2144 2147 2142 2142 2142 9999 9999 9999 9999 9999 9999 9999 9999 2142 2136 2140 2144 2147 2143 2142 2142
DAC Channels
Each DAC channel produces an output voltage in the 0 to +10V range. DAC terminals are on P5 and P10. Even numbered terminals next to DAC terminals are connected to ground.
DAC output registers have 12 data bits (bits 11:0) and one control bit (bit 15). Bits 14:12 are reserved. The control bit is used for synchronization of output voltage updates across multiple channels if necessary and for ensuring software compliance with hardware requirements. When a 1 is written to the control bit, DAC data is sent to all channels even if it has not been changed since the last update. After an update is initiated, software can read the control bit to see if the system is still busy. Further writes of DAC values while the hardware is busy will result in undefined behavior. The update process takes approximately 3 microseconds.
When 0 is written to the control bit, the DAC values are updated internally in the FPGA but not transferred to the DAC. Thus any set of channels can be updated simultaneously by only writing a one on the final write.
The DAC channels can be controlled through ts8820ctl:
ts8820ctl --setdac=1 --mvolts=500
H-Bridges
The TS-8820 supports 2 H-bridges on terminal block P2. One bridge drives terminals 1 and 2, and the second drives terminals 3 and 4. Each pair of terminals can be connected directly to a DC motor. Each H-bridge can supply up to 2.8A of current.
Isolated CAN Port
An isolated CAN port is available on P8. CAN high and low lines are on terminals 11 and 12, respectively. The common CAN ground is on terminal 10.
Isolated RS-232
An isolated RS-232 port is on P8, with TX on terminal 7 and RX on terminal 8. The RS-232 port is driven by macrocontroller UART 1.
Isolated RS-485
An isolated RS-485 port is on P8. Terminals 5 and 6 are the + and - lines, respectively. The RS-485 port is driven by macrocontroller UART 0.
Relays
Terminal block P7 is connected to 4 SPDT relays. Each relay has a COM line which is always connected to either the NC line (relay not activated) or the NO line (relay activated). The 4 relays are controlled by the following DIO.
{{ class=wikitable ! Relay ! DIO |- | 1 | DIO_8 |- | 2 | DIO_7 |- | 3 | DIO_6 |- | 4 | DIO_4 |}
These are not toggled through the TS-8820 FPGA, or through ts8820ctl. You can control these using tsctl or by using the setdiopin function. For example:
# This only needs to be run if you are in debian
source /initrd/ts.subr
# Enable each relay
setdiopin 8 1
setdiopin 7 1
setdiopin 6 1
setdiopin 4 1
Power Supply
If PoE is not used, power must be supplied on terminal block P2. Supply an external ground on terminal 10, 11, and/or 12. Supply +10V to +30V on terminal 7, 8, and/or 9.
LEDS
The TS-8820 has 27 LED indicators. Most are used to provide instant visual confirmation of the states of DIO and relays. Each LED is labeled on the silkscreen.
LED5 to LED8 indicate relay 1 to relay 4 are activated, respectively.
LED9 to LED16 correspond with digital inputs 1 to 8.
LED17 to LED20 correspond with digital outputs 1 to 4.
LED21 to LED26 correspond with digital inputs 9 to 14.
LED27 and LED28 correspond with digital outputs 5 and 6.
LED3 indicates power is supplied to the TS-8820. LED1 and LED4 are connected to the standard red and green LED lines used on most TS-SOCKET systems.
Connectors
Terminal Blocks
|
|
|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
Ethernet Connector
The TS-8820 can connect to any Ethernet LAN. Ethernet is fully supported by any TS-SOCKET macrocontroller. The Ethernet connector includes LEDs indicating link and activity. The link LED should be on whenever the TS-8820 is powered and connected to a LAN. This connector allows the TS-8820 to be powered by PoE.
USB Host
The USB is available on two ports as a USB 2.0 host.
 |
|
DB9 Connector
|
|
Register Map
Most of the access to the IO should be abstracted by ts8820ctl and ts8820.c, but you can also access these IO directly through the MUXBUS registers.
| Offset | Bits | Description |
|---|---|---|
| 0x0 | 15:0 | Model ID: Reads 0x8820 |
| 0x2 | 15:8 | Reserved |
| 7 | H-bridge 2 enable (contacts go high-Z otherwise) | |
| 6 | H-bridge 1 enable (contacts go high-Z otherwise) | |
| 5 | H-bridge 2 direction | |
| 4 | H-bridge 1 direction | |
| 3:0 | FPGA Revision | |
| 0x4 | 15:14 | Reserved |
| 13:0 | Digital inputs 14:1 | |
| 0x6 | 15:10 | Reserved |
| 9:0 | SRAM Page register | |
| 0x8 | 15:12 | Reserved |
| 11:6 | Override Digital Outputs 6:1 with PWM | |
| 5:0 | Digital Output Values 6:1 | |
| 0xa | 15:0 | Reserved |
| 0xc | 15:0 | Reserved |
| 0xe | 15:0 | Reserved |
| 0x10 | 15:13 | PWM #1 Prescaler |
| 12:0 | PWM #1 Duty Cycle | |
| 0x12 | 15:13 | PWM #2 Prescalar |
| 12:0 | PWM #2 Duty Cycle | |
| 0x14 | 15:13 | PWM #3 Prescaler |
| 12:0 | PWM #3 Duty Cycle | |
| 0x16 | 15:13 | PWM #4 Prescaler |
| 12:0 | PWM #4 Duty Cycle | |
| 0x18 | 15:13 | PWM #5 Prescaler |
| 12:0 | PWM #5 Duty Cycle | |
| 0x1a | 15:13 | PWM #6 Prescaler |
| 12:0 | PWM #6 Duty Cycle | |
| 0x1c | 15:13 | PWM #7 Prescaler |
| 12:0 | PWM #7 Duty Cycle | |
| 0x1e | 15:13 | PWM #8 Prescaler |
| 12:0 | PWM #8 Duty Cycle | |
| 0x20 | 15:0 | Pulse Counter #1 |
| 0x22 | 15:0 | Pulse Counter #2 |
| 0x24 | 15:0 | Pulse Counter #3 |
| 0x26 | 15:0 | Pulse Counter #4 |
| 0x28 | 15:0 | Pulse Counter #5 |
| 0x2a | 15:0 | Pulse Counter #6 |
| 0x2c | 15:0 | Pulse Counter #7 |
| 0x2e | 15:0 | Pulse Counter #8 |
| 0x30 | 15:0 | Pulse Counter #9 |
| 0x32 | 15:0 | Pulse Counter #10 |
| 0x34 | 15:0 | Pulse Counter #11 |
| 0x36 | 15:0 | Pulse Counter #12 |
| 0x38 | 15:0 | Pulse Counter #13 |
| 0x3a | 15:0 | Pulse Counter #14 |
| 0x3c | 15:0 | Reserved |
| 0x3e | 15:0 | Reserved |
| 0x80 | 15:0 | ADC Core ID (reads 0xadc1) |
| 0x82 | 15:8 | ADC Channel Mask (0 = do not save channel data) |
| 7:6 | Highest number chip to use (0-3) | |
| 5 | 1 = Force standby | |
| 4 | 1 = Use standby between samples to save power | |
| 3 | 1 = Smart DMA IRQ mode | |
| 2 | 1 = Enable IRQ | |
| 1 | 1 = Collect samples, 0 = stop | |
| 0 | 1 = Reset ADC chips and all FIFOs | |
| 0x84 | 15 | 1 = There has been a FIFO overflow since last reset |
| 14:0 | Number of samples available to be read | |
| 0x86 | 15:0 | Sample Data (RO) |
| 0x88 | 15:0 | Sampling period LSB (RW) |
| 0x8a | 15:0 | Sampling period MSB (RW) |
| 0x8c | 15:0 | IRQ Threshold (RW) |
| 0x8e | 15:0 | DMA transfer size for smart mode (RW) (TODO) |
| 0x90 | 15:0 | Reserved |
| 0x92 | 15:0 | Reserved |
| 0x94 | 15:0 | Reserved |
| 0x96 | 15:0 | Reserved |
| 0x98 | 15:0 | Reserved |
| 0x9a | 15:0 | Reserved |
| 0x9c | 15:0 | Reserved |
| 0x9e | 15:0 | Reserved |
| 0xa0 | 15:0 | DAC 1 Control Register |
| 0xa2 | 15:0 | DAC 2 Control Register |
| 0xa4 | 15:0 | DAC 3 Control Register |
| 0xa6 | 15:0 | DAC 4 Control Register |