TS-CAN1: Difference between revisions

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|-
|-
| 150-157
| 150-157
| OFF
| Off
| OFF
| Off
|-
|-
| 158-15F
| 158-15F
| ON
| On
| OFF
| Off
|-
|-
| 160-167
| 160-167
| OFF
| Off
| ON
| On
|-
|-
| 168-16F
| 168-16F
| ON
| On
| ON
| On
|}
|}


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|-
|-
| None
| None
| OFF
| Off
| OFF
| Off
|-
|-
| IRQ5
| IRQ5
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| 10
| 10
| X
| X
|}
= PLD Register Map =
{| class="wikitable"
|-
! IO Address
! Description
! Access
! Details
|-
| Base + 0
| Board Identifier #1
| R
| Fixed hex value: 0xF6
|-
| Base + 1
| Board Identifier #2
| R
| Fixed hex value: 0xB9
|-
| Base + 2
| PLD Version Register
| R
| Fixed value
|-
| Base + 3
| LED control/status
| RW
|
{| class="wikitable"
|-
! Bit
! Description
|-
| 0
| LED (1=on, 0=off)
|}
|-
| Base + 4
| Page selection register
| RW
|
{| class="wikitable"
|-
! Bit
! Description
|-
| 0-1
| Select one-of-four pages for SJA1000 access.  This allows all 128 registers to be accessed using only 32 bytes of I/O space.  Default to all zeroes.  See SJA1000 I/O page selection register.
|-
| 2-7
| Reserved
|-
|}
|-
| Base + 5
| Mode control Register
| RW
|
{| class="wikitable"
|-
! Bit
! Description
|-
| 0
| LSB of 3 bit address select register.  See SJA1000 I/O address selection.
|-
| 1
| Middle of 3 bit address select register.
|-
| 2
| MSB of 3 bit address select register.
|-
| 3-4
| Reserved
|-
| 5
| If set, it allows the sharing of IRQ6 and IRQ7.  It can only be set for TS ARM platforms and sharing can only be used for IRQ6 and IRQ7.
|-
| 6
| If set, it enables SJA1000 to appear in IO space location determined by mode bits 0-2.  Also enables the page selection register (Base + 4) to be used.
|-
| 7
| Reserved
|}
|-
| Base + 6
| Jumper Status
| R
|
{| class="wikitable"
|-
! Bit
! Description
|-
| 0
| Reserved
|-
| 1
| Jumper 1 (1=on, 0=off)
|-
| 2
| Jumper 2 (1=on, 0=off)
|-
| 3
| Jumper 3 (1=on, 0=off)
|-
| 4
| Jumper 4 (1=on, 0=off)
|-
| 5
| Jumper 5 (1=on, 0=off)
|-
| 6-7
| Reserved
|}
|-
| Base + 7
| Reserved
|
|
|}
|}

Revision as of 17:33, 30 June 2011

TS-CAN1
Ts-can1.jpg
Documents
Schematic
Manual
Ocera CANOpen Manual

Overview

The TS-CAN1 is a PC104 board which provides 1 port to connect to CAN1.1 and CAN2.0b networks.

Hardware Configuration

Jumper settings for I/O Addr selection

IO Address JP1 JP2
150-157 Off Off
158-15F On Off
160-167 Off On
168-16F On On

Jumper settings for IRQ Selection

IRQ JP4 JP5
None Off Off
IRQ5 On On
IRQ6 On Off
IRQ7 Off On

CAN 10 Pin Header

Pin Number Signal
1 X
2 CANL
3 GND
4 X
5 X
6 GND
7 CANH
8 X
9 X
10 X

PLD Register Map

IO Address Description Access Details
Base + 0 Board Identifier #1 R Fixed hex value: 0xF6
Base + 1 Board Identifier #2 R Fixed hex value: 0xB9
Base + 2 PLD Version Register R Fixed value
Base + 3 LED control/status RW
Bit Description
0 LED (1=on, 0=off)
Base + 4 Page selection register RW
Bit Description
0-1 Select one-of-four pages for SJA1000 access. This allows all 128 registers to be accessed using only 32 bytes of I/O space. Default to all zeroes. See SJA1000 I/O page selection register.
2-7 Reserved
Base + 5 Mode control Register RW
Bit Description
0 LSB of 3 bit address select register. See SJA1000 I/O address selection.
1 Middle of 3 bit address select register.
2 MSB of 3 bit address select register.
3-4 Reserved
5 If set, it allows the sharing of IRQ6 and IRQ7. It can only be set for TS ARM platforms and sharing can only be used for IRQ6 and IRQ7.
6 If set, it enables SJA1000 to appear in IO space location determined by mode bits 0-2. Also enables the page selection register (Base + 4) to be used.
7 Reserved
Base + 6 Jumper Status R
Bit Description
0 Reserved
1 Jumper 1 (1=on, 0=off)
2 Jumper 2 (1=on, 0=off)
3 Jumper 3 (1=on, 0=off)
4 Jumper 4 (1=on, 0=off)
5 Jumper 5 (1=on, 0=off)
6-7 Reserved
Base + 7 Reserved
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