TS-CAN1: Difference between revisions

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= Hardware Configuration =
= Hardware Configuration =
== Jumper settings for I/O Address selection ==
== Jumper settings for I/O Address Selection ==
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Revision as of 23:18, 30 June 2011

TS-CAN1
Ts-can1.jpg
Documents
Schematic
Manual
Ocera CANOpen Manual

Overview

The TS-CAN1 is a PC104 board which provides 1 port to connect to CAN1.1 and CAN2.0b networks.

Hardware Configuration

Jumper settings for I/O Address Selection

IO Address JP1 JP2
150-157 Off Off
158-15F On Off
160-167 Off On
168-16F On On

Jumper settings for IRQ Selection

IRQ JP4 JP5
None Off Off
IRQ5 On On
IRQ6 On Off
IRQ7 Off On

CAN 10 Pin Header

Pin Number Signal
1 X
2 CANL
3 GND
4 X
5 X
6 GND
7 CANH
8 X
9 X
10 X

PLD Register Map

IO Address Description Access Details
Base + 0 Board Identifier #1 R Fixed hex value: 0xF6
Base + 1 Board Identifier #2 R Fixed hex value: 0xB9
Base + 2 PLD Version Register R Fixed value
Base + 3 LED control/status RW
Bit Description
0 LED (1=on, 0=off)
Base + 4 Page selection register RW
Bit Description
2-7 Reserved
0-1 Select one-of-four pages for SJA1000 access. This allows all 128 registers to be accessed using only 32 bytes of I/O space. Default to all zeroes. See SJA1000 I/O page selection register.
Base + 5 Mode control Register RW
Bit Description
7 Reserved
6 If set, it enables SJA1000 to appear in IO space location determined by mode bits 0-2. Also enables the page selection register (Base + 4) to be used.
5 If set, it allows the sharing of IRQ6 and IRQ7. It can only be set for TS ARM platforms and sharing can only be used for IRQ6 and IRQ7.
3-4 Reserved
2 MSB of 3 bit address select register.
1 Middle of 3 bit address select register.
0 LSB of 3 bit address select register. See SJA1000 I/O address selection.
Base + 6 Jumper Status R
Bit Description
6-7 Reserved
5 Jumper 5 (1=on, 0=off)
4 Jumper 4 (1=on, 0=off)
3 Jumper 3 (1=on, 0=off)
2 Jumper 2 (1=on, 0=off)
1 Jumper 1 (1=on, 0=off)
0 Reserved
Base + 7 Reserved

SJA1000 IO Page Selection Reg

Page Registers Bit1 Bit0
1 00-1f 0 0
2 20-3f 0 1
3 40-5f 1 0
4 60-7f 1 1

SJA1000 IO Address Selection Register

Address Range Bit2 Bit1 Bit0
100-11f 0 0 0
120-13f 0 0 1
180-19f 0 1 0
1A0-1Bf 0 1 1
200-21f 1 0 0
240-25f 1 0 1
280-29f 1 1 0
320-33f 1 1 1

PC104 Compatibility Grid

X86

SBC Status Notes
TS-5700 X
TS-5600 X
TS-5500 X
TS-5400 X
TS-5300 X
TS-3400
TS-3300
TS-3200
TS-3100

ARM

SBC Status Notes
TS-7800
TS-7558
TS-7553
TS-7552
TS-7550
TS-7500
TS-7400
TS-7395/TS-7390
TS-7370
TS-7350
TS-7300
TS-7260
TS-7250
TS-7200

FAQ