TS-ENC730: Difference between revisions

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|data1        = [http://www.embeddedarm.com/products/board-detail.php?product=TS-ENC730 Product Page]
|data1        = [http://www.embeddedarm.com/products/board-detail.php?product=TS-ENC730 Product Page]
|header2      = Documents
|header2      = Documents
|data3        = [http://www.embeddedarm.com/documentation/ts-enc720-782-schematic.pdf Schematic]
|data3        = [http://www.embeddedarm.com/documentation/ts-enc730-732-schematic.pdf Schematic]  
|data4        = [http://www.embeddedarm.com/documentation/ts-enc720-mechanical.pdf Mechanical Drawing]
}}
}}


= Overview =  
= Overview =  
The TS-ENC720 metal enclosure is made to house the [[TS-7200]], [[TS-7250]], [[TS-7260]], [[TS-7350]], [[TS-7800]], [[TS-8100]], or [[TS-8160]] Single Board Computer and two PC/104 peripheral boards. The switching power regulator efficiently converts 8-30 VDC input (8-38 VDC for the [[TS-7800]]) into regulated +5 VDC required by the SBC.
The TS-ENC730 metal enclosure is made to house the [[TS-7300]] Single Board Computer and up to two PC/104 peripheral boards. The internal power regulator efficiently converts unregulated 7-28 VDC input into regulated +5 VDC as required by the SBC. Sleep mode allows current drain of 200 microAmps with programmable sleep periods. The TS-ENC730 also brings out some features implemented on the [[TS-7300]] FPGA, such as the SJA1000 CAN core, PWM for the DAC lines, 800x600 VGA Video, second ethernet port, additional serial ports, etc. In addition, the TS-ENC730 includes the [[TS-732]] daughter board for the [[TS-7300]] onboard FPGA. The AVR microcontroller on the [[TS-732]] implements ADC/GPIO/LEDs extra functionalities. Also, the physical layer for the CAN bus is provided by the [[TS-732]].


Note that the [[TS-DIO64]] and the [[TS-9700]] with the DAC option both have connectors that do not fit into the TS-ENC720.  The second Ethernet or reset button of the [[TS-8100]] or [[TS-8160]] is not compatible with this enclosure.
= Features =
The TS-ENC730 Rugged Enclosure provides extra functions, including power converter,
AVR microcontroller daughter board and CAN Phy. Additional features include:
*8-28 VDC power input
*User programmable low power sleep mode (300 uA)
*Surge suppression on power input
*Terminal strip with 8 I/O
*4 channel 10 bit ADC 0V - 5V (12-16 bits effective*)
*2 channel 12 bit high power DAC 0V - 10V (sync/source 300mA)
*4 high current GPIO pins (sync/source 400 mA)
*5-8 COM ports
*Two software controlled LEDs
*Status LEDs for both Ethernet ports
*Optional CAN bus port with Linux driver available
*Linux Application available for ADC/DAC/GPIO/LEDs control
*Sturdy metal design reduces noise


The dimensions of the TS-ENC720 are 2.5" x 4.375" x 5.375.
= TS-ENC730 FPGA =
The TS-ENC730 includes a [[TS-7300]] FPGA core designed specially for the TS-ENC730
and the [[TS-732]] daughter companion board. This FPGA core talks to the AVR
Microcontroller on the [[TS-732]] via a UART interface, making use of the 8x baud clock
reference provided by the AVR. This FPGA core also implements a SJA1000 CAN
controller and 2 PWM channels for the [[TS-732]] DAC circuitry. The registers that control
these functions appear in the memory space of the ARM9 processor dedicated for the
FPGA functions, therefore they can be accessed through the Linux OS and programming.
The base address used is 0x7200_0400 and the register are 16-bit wide.


= COM2 and COM3 =
== Register Map ==
Two standard DB-9 connectors are brought out for additional COM ports, DIO, or A/D conversion.  The DB-9 headers are connected straight to the enclosed SBC.  COM2 header is designed to connect to the A/D (MAX197 on [[TS-7200]]/[[TS-7250]]) header on the enclosed SBC and COM3 is designed for the DIO1 (or XDIO/DIO2 on the [[TS-7260]]) header of the enclosed SBC.  Both COM2 and COM3 are set up to connect to COM headers on the enclosed SBC.
{| class="wikitable"
|-
! I/O Address
! Description
! Data Bits
|-
| Base + 0
| Control Register
| bits 3:15 – reserved


{{warning|Connecting both RS-232 signals and DIO or A/D to the same COM port may cause irreversible damage to the SBC.}}
bit 2: CAN controller enable
 
bit 1: PWM channel #1 enable
 
bit 0: PWM channel #0 enable
|-
| Base + 2
| PWM channel #0 high-time
|
|-
| Base + 4
| PWM channel #0 low-time
|
|-
| Base + 6
| PWM channel #1 high-time
|
|-
| Base + 8
| PWM channel #1 low-time
|
|-
| Base + A
| AVR clock reference
|
|-
| Base + C
| AVR UART STAT register
|
|-
| Base + E
| AVR UART RXDAT/TXDAT register
|
|-
| Base + 100
| CAN controller regs start
| SJA1000: 256 byte x 8bit registers
|}
 
The AVR clock reference represents the current frequency/2 of the clock coming
out the AVR. Nominally this should be 100Khz. Register value is updated twice per
second.

Revision as of 00:43, 10 August 2011

TS-ENC730
Ts-enc730.jpg
Product Page
Documents
Schematic

Overview

The TS-ENC730 metal enclosure is made to house the TS-7300 Single Board Computer and up to two PC/104 peripheral boards. The internal power regulator efficiently converts unregulated 7-28 VDC input into regulated +5 VDC as required by the SBC. Sleep mode allows current drain of 200 microAmps with programmable sleep periods. The TS-ENC730 also brings out some features implemented on the TS-7300 FPGA, such as the SJA1000 CAN core, PWM for the DAC lines, 800x600 VGA Video, second ethernet port, additional serial ports, etc. In addition, the TS-ENC730 includes the TS-732 daughter board for the TS-7300 onboard FPGA. The AVR microcontroller on the TS-732 implements ADC/GPIO/LEDs extra functionalities. Also, the physical layer for the CAN bus is provided by the TS-732.

Features

The TS-ENC730 Rugged Enclosure provides extra functions, including power converter, AVR microcontroller daughter board and CAN Phy. Additional features include:

  • 8-28 VDC power input
  • User programmable low power sleep mode (300 uA)
  • Surge suppression on power input
  • Terminal strip with 8 I/O
  • 4 channel 10 bit ADC 0V - 5V (12-16 bits effective*)
  • 2 channel 12 bit high power DAC 0V - 10V (sync/source 300mA)
  • 4 high current GPIO pins (sync/source 400 mA)
  • 5-8 COM ports
  • Two software controlled LEDs
  • Status LEDs for both Ethernet ports
  • Optional CAN bus port with Linux driver available
  • Linux Application available for ADC/DAC/GPIO/LEDs control
  • Sturdy metal design reduces noise

TS-ENC730 FPGA

The TS-ENC730 includes a TS-7300 FPGA core designed specially for the TS-ENC730 and the TS-732 daughter companion board. This FPGA core talks to the AVR Microcontroller on the TS-732 via a UART interface, making use of the 8x baud clock reference provided by the AVR. This FPGA core also implements a SJA1000 CAN controller and 2 PWM channels for the TS-732 DAC circuitry. The registers that control these functions appear in the memory space of the ARM9 processor dedicated for the FPGA functions, therefore they can be accessed through the Linux OS and programming. The base address used is 0x7200_0400 and the register are 16-bit wide.

Register Map

I/O Address Description Data Bits
Base + 0 Control Register bits 3:15 – reserved

bit 2: CAN controller enable

bit 1: PWM channel #1 enable

bit 0: PWM channel #0 enable

Base + 2 PWM channel #0 high-time
Base + 4 PWM channel #0 low-time
Base + 6 PWM channel #1 high-time
Base + 8 PWM channel #1 low-time
Base + A AVR clock reference
Base + C AVR UART STAT register
Base + E AVR UART RXDAT/TXDAT register
Base + 100 CAN controller regs start SJA1000: 256 byte x 8bit registers 
The AVR clock reference represents the current frequency/2 of the clock coming
out the AVR. Nominally this should be 100Khz. Register value is updated twice per
second.
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