TS-POE100

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TS-POE100
Ts-poe100.jpg
Documents
Schematic

Overview

The TS-POE100 is a PC/104 peripheral board (standard format) that provides a 10/100 Ethernet port integrated with a Power-over-Ethernet splitter circuit, which is capable to provide up to 12W of power through the PC/104 bus.

The TS-POE100 features a Linear Technology LTC4267 PoE chip fully compatible with the IEEE 802.3af specification. The TS-POE100 is a Power-over-Ethernet splitter interface that provides up to 12W (2.4A @ 5V) to external devices (class 3 devices). The internal switching-regulator delivers regulated 5VDC to the PC/104 connector, enabling a complete stackable SBC system to be powered.

In addition, the TS-POE100 provides an integrated 10/100 ethernet port through the ASIX AX88796B embedded MAC with on-chip PHY. It interfaces with the PC/104 connector via 16-bit data bus and the register map is NE2000 compatible. The ASIX solution features Wake-on-LAN functionality, enabling the Ethernet chip to enter in sleep mode with programmed wake-up on the reception of a magic network package. Once integrated with the PoE, this function allows a complete SBC system to enter power-save mode and to wake-up through the network whenever wanted.

Hardware Configuration

The TS-POE100 jumpers select one-of-three IRQ lines and one-of-four I/O address regions. Also, it is possible to do PC/104 16-bit access using only the 64-pin PC/104 connector in ARM mode if the ARM jumper is ON. Jumpers IRQ5, IRQ6 and IRQ7 selects the desired ISA IRQ line for the TS-POE100 MAC.

I/O Address

The PLD and MAC I/O address locations can be configured using jumpers Add1 and Add2 according to the table below:

PLD I/O MAC I/O Add1 Add2
0x100 0x200 Off Off
0x110 0x240 On Off
0x120 0x300 Off On
0x130 0x340 On On

Base Register Map

The TS-POE100 has 4 registers of 4-bits each which appear implemented on the PLD.

PLD I/O MAC I/O Add1 Add2
0x100 0x200 Off Off
0x110 0x240 On Off
0x120 0x300 Off On
0x130 0x340 On On