TS-SDCORE2: Difference between revisions
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(Created page with "The TS-SDCORE2 is a lightweight SD controller that bitbangs most SD access, but switches to an FPGA state machine for reads/writes. It allows control over multiple devices by...") |
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| | | Stream 4-bit read/write on sd_dat bus with automatic crc/ack/cardready checks <ref>Outputs from the LSB byte to the MSB byte</ref> | ||
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Revision as of 10:23, 25 March 2022
The TS-SDCORE2 is a lightweight SD controller that bitbangs most SD access, but switches to an FPGA state machine for reads/writes. It allows control over multiple devices by muxing the SD clock between cards, while leaving the others gated.
Register | Bits | Description | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | 31:19 | Reserved | |||||||||
18:16 | clksel - Set which LUN (0-4) gets clocks. The others will remain gated. | ||||||||||
15:14 | Reserved | ||||||||||
13 | fast_en - Set to allow 0 latency writes for bursts | ||||||||||
12 | wrmult_en - Enable write multiple. After a write makes the core wait for CRC ack and card not busy, and continue writing | ||||||||||
11 | rdmult_en - Enable read multiple. after a read makes the core wait for CRC ack and card not busy, then continue reading | ||||||||||
10:8 | Reserved | ||||||||||
7:6 |
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5 | SD Clock (1 = pulse clock, 0 keep low) | ||||||||||
4 | SD_CMD output data (1 high, 0 low) | ||||||||||
3:0 | SD_DAT output data (1 high, 0 low) | ||||||||||
0x4 | 31:0 | Stream 4-bit read/write on sd_dat bus with automatic crc/ack/cardready checks [2] |