TS-SDCORE2: Difference between revisions
From embeddedTS Manuals
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{| class=wikitable | {| class=wikitable | ||
|- | |- | ||
! Register | ! Register | ||
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! Description | ! Description | ||
|- | |- | ||
| rowspan=11 | 0x0 | | rowspan=11 | 0x0 <ref> Writing byte 0 with any value has the side effect of clearing a CRC error, and resets the number of clocks for an access to 0. </ref> | ||
| 31:19 | | 31 | ||
| Reserved | |||
|- | |||
| 30 | |||
| On TS-SDCORE 2, this bit is stuck 0. On TS-SDCORE 1, this bit is read/write. This can be used for detecting which hardware core is present. | |||
|- | |||
| 29:19 | |||
| Reserved | | Reserved | ||
|- | |- | ||
Line 15: | Line 20: | ||
| clksel - Set which LUN (0-4) gets clocks. The others will remain gated. | | clksel - Set which LUN (0-4) gets clocks. The others will remain gated. | ||
|- | |- | ||
| 15 | | 15 | ||
| Reserved | | Reserved | ||
|- | |||
| 14 | |||
| timeout - Card exceeded number of expected clocks before returning an answer. Cleared on read. | |||
|- | |- | ||
| 13 | | 13 | ||
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| rdmult_en - Enable read multiple. after a read makes the core wait for CRC ack and card not busy, then continue reading | | rdmult_en - Enable read multiple. after a read makes the core wait for CRC ack and card not busy, then continue reading | ||
|- | |- | ||
| 10 | | 10 | ||
| | | crc_err - Cleared on read | ||
|- | |||
| 9 | |||
| sd_wprot - Card write protect status - 1 = write protect enabled, 0 = write protect off | |||
|- | |||
| 8 | |||
| sd_detect - 1 if a card is detected | |||
|- | |- | ||
| 7:6 | | 7:6 | ||
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| 0x8 | | 0x8 | ||
| 31:0 | | 31:0 | ||
| Stream 1-bit read/write to sd_cmd. Shifts out starting from bit 31 to 0, then sends a crc7. | | Stream 1-bit read/write to sd_cmd. Shifts out starting from bit 31 to 0, then sends a crc7 (40 clocks total). | ||
|- | |- | ||
| 0xc | | 0xc |
Revision as of 10:51, 25 March 2022
The TS-SDCORE2 is a lightweight SD controller that bitbangs most SD access, but switches to an FPGA state machine for reads/writes. It allows control over multiple devices by muxing the SD clock between cards, while leaving the others gated.
Register | Bits | Description | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
0x0 [1] | 31 | Reserved | |||||||||
30 | On TS-SDCORE 2, this bit is stuck 0. On TS-SDCORE 1, this bit is read/write. This can be used for detecting which hardware core is present. | ||||||||||
29:19 | Reserved | ||||||||||
18:16 | clksel - Set which LUN (0-4) gets clocks. The others will remain gated. | ||||||||||
15 | Reserved | ||||||||||
14 | timeout - Card exceeded number of expected clocks before returning an answer. Cleared on read. | ||||||||||
13 | fast_en - Set to allow 0 latency writes for bursts | ||||||||||
12 | wrmult_en - Enable write multiple. After a write makes the core wait for CRC ack and card not busy, and continue writing | ||||||||||
11 | rdmult_en - Enable read multiple. after a read makes the core wait for CRC ack and card not busy, then continue reading | ||||||||||
10 | crc_err - Cleared on read | ||||||||||
9 | sd_wprot - Card write protect status - 1 = write protect enabled, 0 = write protect off | ||||||||||
8 | sd_detect - 1 if a card is detected | ||||||||||
7:6 |
| ||||||||||
5 | SD Clock (1 = pulse clock, 0 keep low) | ||||||||||
4 | SD_CMD output data (1 high, 0 low) | ||||||||||
3:0 | SD_DAT output data (1 high, 0 low) | ||||||||||
0x4 | 31:0 | Stream 4-bit read/write on sd_dat bus with automatic crc/ack/cardready checks [3] | |||||||||
0x8 | 31:0 | Stream 1-bit read/write to sd_cmd. Shifts out starting from bit 31 to 0, then sends a crc7 (40 clocks total). | |||||||||
0xc | 31:0 | This register allows detection of 32-bit tssdcorev2 vs 8-bit ts-sdcore v2 |