TS-SDCORE2
From embeddedTS Manuals
The TS-SDCORE2 is a lightweight SD controller that bitbangs most SD access, but switches to an FPGA state machine for reads/writes. It allows control over multiple devices by muxing the SD clock between cards, while leaving the others gated.
| Register | Bits | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 [1] | 31 | Reserved | |||||||||
| 30 | On TS-SDCORE 2, this bit is stuck 0. On TS-SDCORE 1, this bit is read/write. This can be used for detecting which hardware core is present. | ||||||||||
| 29:19 | Reserved | ||||||||||
| 18:16 | clksel - Set which LUN (0-4) gets clocks. The others will remain gated. | ||||||||||
| 15 | Reserved | ||||||||||
| 14 | timeout - Card exceeded number of expected clocks before returning an answer. Cleared on read. | ||||||||||
| 13 | fast_en - Set to allow 0 latency writes for bursts | ||||||||||
| 12 | wrmult_en - Enable write multiple. After a write makes the core wait for CRC ack and card not busy, and continue writing | ||||||||||
| 11 | rdmult_en - Enable read multiple. after a read makes the core wait for CRC ack and card not busy, then continue reading | ||||||||||
| 10 | crc_err - Cleared on read | ||||||||||
| 9 | sd_wprot - Card write protect status - 1 = write protect enabled, 0 = write protect off | ||||||||||
| 8 | sd_detect - 1 if a card is detected | ||||||||||
| 7:6 |
| ||||||||||
| 5 | SD Clock (1 = pulse clock, 0 keep low) | ||||||||||
| 4 | SD_CMD output data (1 high, 0 low) | ||||||||||
| 3:0 | SD_DAT output data (1 high, 0 low) | ||||||||||
| 0x4 | 31:0 | Stream 4-bit read/write on sd_dat bus with automatic crc/ack/cardready checks [3] | |||||||||
| 0x8 | 31:0 | Stream 1-bit read/write to sd_cmd. Shifts out starting from bit 31 to 0, then sends a crc7 (40 clocks total). | |||||||||
| 0xc [4] | 31:7 | Reserved | |||||||||
| 6 | This is set to 1 when accessed as a 32-bit bus, or 0 when accessed as an 8-bit bus. | ||||||||||
| 5:0 | Reserved |
- ↑ Writing byte 0 with any value has the side effect of clearing a CRC error, and resets the number of clocks for an access to 0.
- ↑ If sd_oe = 0x0, sd_clk = 0, sd_lcmd = 0, and sd_ldat = 0, this also turns off power to the SD card.
- ↑ Outputs from the LSB byte to the MSB byte
- ↑ A write of any value to this register sets the state machine to wait for CRC ack, and wait for card not busy