TS-TPC-7990 FPGA GPIO Table: Difference between revisions
From embeddedTS Manuals
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The FPGA | The FPGA GPIO can also be accessed through the sysfs API. These are available at GPIOs 224 to 255. Not all of the reserved pins are used on this design, but they will be reserved by the kernel. | ||
{| class="wikitable sortable" | {| class="wikitable sortable" | ||
|- | |- | ||
! | ! Name | ||
! GPIO Number | ! GPIO Number | ||
! Default Crossbar Mode | ! Default Crossbar Mode | ||
! Location | ! Location | ||
|- | |- | ||
| | | UART3_RXD (TTYMXC2_RXD) | ||
| | | 224 | ||
| | | COM3_RXD_232_3V (13) | ||
| CPU pin EIM_D25 (89) | |||
|- | |- | ||
| | | UART5_RXD (TTYMXC4_RXD) | ||
| | | 225 | ||
| | | COM3_RXD_232_3V (12) | ||
| CPU pin KEY_ROW1 (105) | |||
|- | |- | ||
| | | UART3_CTS (TTYMXC2_CTS) | ||
| | | 226 | ||
| | | GPIO (31) | ||
| CPU pin EIM_D31 (95) | |||
|- | |- | ||
| | | UART4_RXD (TTYMXC3_RXD) | ||
| | | 227 | ||
| | | RXD3_485_3V (10) | ||
| CPU pin KEY_ROW0 (103) | |||
|- | |||
| UART2_CTS (TTYMXC1_CTS) | |||
| 228 | |||
| BT_RTS (1) | |||
| CPU pin SD4_DAT6 (46) | |||
|- | |||
| UART3_RTS (TTYMXC2_RTS) | |||
| 229 | |||
| GPIO (31) | |||
| CPU pin EIM_D30 (94) | |||
|- | |||
| DIO_8 | |||
| 230 | |||
| GPIO (31) | |||
| HD8 pin 25 | |||
|- | |||
| DIO_9 | |||
| 231 | |||
| GPIO (31) | |||
| HD8 pin 23 | |||
|- | |||
| TXD1_485 | |||
| 232 | |||
| TTYMAX1_TXD (19) | |||
| HD1 pin 1/6 (RS485+-) | |||
|- | |||
| TXD2_485 | |||
| 233 | |||
| TTYMAX0_TXD (16) | |||
| HD2 pin 1/6 (RS485+-) | |||
|- | |||
| TXD3_485 | |||
| 234 | |||
| TTYMXC3_TXD (14) | |||
| HD3 pin 1/6 (RS485+-) | |||
|- | |||
| TXEN1_485 | |||
| 235 | |||
| TTYMAX1_TXEN (20) | |||
| HD1 RS485 TX enable | |||
|- | |||
| TXEN2_485 | |||
| 236 | |||
| TTYMAX0_TXEN (17) | |||
| HD2 RS485 TX enable | |||
|- | |||
| BT_EN | |||
| 237 | |||
| GPIO Only | |||
| Register | |||
|- | |||
| WL_EN | |||
| 238 | |||
| GPIO Only | |||
| Register | |||
|- | |||
| BT_CTS | |||
| 240 | |||
| TTYMXC1_RTS (6) | |||
| Onboard Bluetooth CTS | |||
|- | |||
| BT_RXD | |||
| 241 | |||
| TTYMXC1_TXD (15) | |||
| Onboard Bluetooth RXD | |||
|- | |||
| UART2_RXD (TTYMXC1_RXD) | |||
| 242 | |||
| BT_TXD (2) | |||
| Onboard Bluetooth TXD | |||
|- | |||
| DIO_0 | |||
| 243 | |||
| GPIO (31) | |||
| HD8 pin 5 | |||
|- | |||
| DIO_1 | |||
| 244 | |||
| GPIO (31) | |||
| HD8 pin 7 | |||
|- | |||
| DIO_2 | |||
| 245 | |||
| GPIO (31) | |||
| HD8 pin 9 | |||
|- | |||
| DIO_3 | |||
| 246 | |||
| GPIO (31) | |||
| HD8 pin 11 | |||
|- | |||
| DIO_4 | |||
| 247 | |||
| GPIO (31) | |||
| HD8 pin 10 | |||
|- | |||
| DIO_5 | |||
| 248 | |||
| GPIO (31) | |||
| HD8 pin 12 | |||
|- | |||
| DIO_6 | |||
| 249 | |||
| GPIO (31) | |||
| HD8 pin 14 | |||
|- | |||
| DIO_7 | |||
| 250 | |||
| GPIO (31) | |||
| HD8 pin 16 | |||
|- | |||
| FPGA_IRQ_1 | |||
| 251 | |||
| GPIO (31) | |||
| CPU pin GPIO_4 (4) | |||
|- | |||
| Reboot | |||
| 254 | |||
| N/A (GPIO only) | |||
| Register | |||
|- | |||
| TTYMAX0_RXD | |||
| 268 | |||
| RXD2_485_3V (9) | |||
| FPGA Generated UART | |||
|- | |||
| TTYMAX1_RXD | |||
| 269 | |||
| RXD1_485_3V (8) | |||
| FPGA Generated UART | |||
|- | |||
| TTYMAX2_RXD | |||
| 270 | |||
| COM1_RXD_232_3V (11) | |||
| FPGA Generated UART | |||
|- | |||
| TXEN3_485 | |||
| 271 | |||
| TTYMXC3_TXEN (26) | |||
| HD3 RS485 TX enable | |||
|- | |||
| COM1_TXD_232_3V | |||
| 272 | |||
| TTYMAX2_TXD (22) | |||
| HD1 pin 3 | |||
|- | |||
| COM2_TXD_232_3V | |||
| 273 | |||
| TTYMXC4_TXD (3) | |||
| HD2 pin 3 | |||
|- | |||
| COM3_TXD_232_3V | |||
| 274 | |||
| TTYMXC2_TXD (4) | |||
| HD3 pin 3 | |||
|- | |||
| COM1_RTS_3V | |||
| 276 | |||
| TTYMAX2_RTS (24) | |||
| HD1 pin 8 | |||
|- | |||
| TTYMAX0_CTS | |||
| 277 | |||
| GPIO (29) | |||
| FPGA Generated UART | |||
|- | |||
| TTYMAX1_CTS | |||
| 278 | |||
| GPIO (29) | |||
| FPGA Generated UART | |||
|- | |||
| TTYMAX2_CTS | |||
| 279 | |||
| GPIO (29) | |||
| FPGA Generated UART | |||
|- | |||
| MT_LCD_PRESENT | |||
| 284 | |||
| GPIO Only | |||
| Register | |||
|- | |||
| EN_SPKR | |||
| 285 | |||
| GPIO Only | |||
| Regulator AMP enable | |||
|} | |} |
Latest revision as of 12:20, 23 August 2016
The FPGA GPIO can also be accessed through the sysfs API. These are available at GPIOs 224 to 255. Not all of the reserved pins are used on this design, but they will be reserved by the kernel.
Name | GPIO Number | Default Crossbar Mode | Location |
---|---|---|---|
UART3_RXD (TTYMXC2_RXD) | 224 | COM3_RXD_232_3V (13) | CPU pin EIM_D25 (89) |
UART5_RXD (TTYMXC4_RXD) | 225 | COM3_RXD_232_3V (12) | CPU pin KEY_ROW1 (105) |
UART3_CTS (TTYMXC2_CTS) | 226 | GPIO (31) | CPU pin EIM_D31 (95) |
UART4_RXD (TTYMXC3_RXD) | 227 | RXD3_485_3V (10) | CPU pin KEY_ROW0 (103) |
UART2_CTS (TTYMXC1_CTS) | 228 | BT_RTS (1) | CPU pin SD4_DAT6 (46) |
UART3_RTS (TTYMXC2_RTS) | 229 | GPIO (31) | CPU pin EIM_D30 (94) |
DIO_8 | 230 | GPIO (31) | HD8 pin 25 |
DIO_9 | 231 | GPIO (31) | HD8 pin 23 |
TXD1_485 | 232 | TTYMAX1_TXD (19) | HD1 pin 1/6 (RS485+-) |
TXD2_485 | 233 | TTYMAX0_TXD (16) | HD2 pin 1/6 (RS485+-) |
TXD3_485 | 234 | TTYMXC3_TXD (14) | HD3 pin 1/6 (RS485+-) |
TXEN1_485 | 235 | TTYMAX1_TXEN (20) | HD1 RS485 TX enable |
TXEN2_485 | 236 | TTYMAX0_TXEN (17) | HD2 RS485 TX enable |
BT_EN | 237 | GPIO Only | Register |
WL_EN | 238 | GPIO Only | Register |
BT_CTS | 240 | TTYMXC1_RTS (6) | Onboard Bluetooth CTS |
BT_RXD | 241 | TTYMXC1_TXD (15) | Onboard Bluetooth RXD |
UART2_RXD (TTYMXC1_RXD) | 242 | BT_TXD (2) | Onboard Bluetooth TXD |
DIO_0 | 243 | GPIO (31) | HD8 pin 5 |
DIO_1 | 244 | GPIO (31) | HD8 pin 7 |
DIO_2 | 245 | GPIO (31) | HD8 pin 9 |
DIO_3 | 246 | GPIO (31) | HD8 pin 11 |
DIO_4 | 247 | GPIO (31) | HD8 pin 10 |
DIO_5 | 248 | GPIO (31) | HD8 pin 12 |
DIO_6 | 249 | GPIO (31) | HD8 pin 14 |
DIO_7 | 250 | GPIO (31) | HD8 pin 16 |
FPGA_IRQ_1 | 251 | GPIO (31) | CPU pin GPIO_4 (4) |
Reboot | 254 | N/A (GPIO only) | Register |
TTYMAX0_RXD | 268 | RXD2_485_3V (9) | FPGA Generated UART |
TTYMAX1_RXD | 269 | RXD1_485_3V (8) | FPGA Generated UART |
TTYMAX2_RXD | 270 | COM1_RXD_232_3V (11) | FPGA Generated UART |
TXEN3_485 | 271 | TTYMXC3_TXEN (26) | HD3 RS485 TX enable |
COM1_TXD_232_3V | 272 | TTYMAX2_TXD (22) | HD1 pin 3 |
COM2_TXD_232_3V | 273 | TTYMXC4_TXD (3) | HD2 pin 3 |
COM3_TXD_232_3V | 274 | TTYMXC2_TXD (4) | HD3 pin 3 |
COM1_RTS_3V | 276 | TTYMAX2_RTS (24) | HD1 pin 8 |
TTYMAX0_CTS | 277 | GPIO (29) | FPGA Generated UART |
TTYMAX1_CTS | 278 | GPIO (29) | FPGA Generated UART |
TTYMAX2_CTS | 279 | GPIO (29) | FPGA Generated UART |
MT_LCD_PRESENT | 284 | GPIO Only | Register |
EN_SPKR | 285 | GPIO Only | Regulator AMP enable |