TS-4800 TS-Socket

The TS-SOCKET System-on-Modules (SoMs) all use two high density 100 pin connectors for power and all I/O. These follow a common pinout for various external interfaces so new modules can be dropped in to lower power consumption or use a more powerful processor. The male connector is on the baseboard, and the female connector is on the SoM. You can find the datasheet for the baseboard's male connector here. This can be ordered from the TS-Socket SoM product page as CN-TSSOCKET-M-10 for a 10 pack, or CN-TSSOCKET-M-100 for 100 pieces, or from the vendor of your choice, the part is an FCI "61083-102402LF".

We have an Eaglecad library available for developing a custom baseboard here. We also provide the entire PCB design for the TS-8200 baseboard here which you can modify for your own design.

In our schematics and our table layout below, we refer to pin 1 from the male connector on the baseboard.

CN1

CN2

Name Pin Pin Name FPGA_JTAG_TMS 1 2 EXT_RESET# FPGA_JTAG_TCK 3 C 4 EN_USB_5V FPGA_JTAG_TDO 5 N 6 SD1_D2 FPGA_JTAG_TDI 7 1 8 SD1_D3 OFF_BD_RESET# 9 10 SD1_CMD Reserved 11 12 SDCARD_3.2V Reserved 13 C 14 SD1_CLK POWER 15 N 16 POWER Reserved 17 1 18 SD1_D0 DISP_DAT08 19 20 SD1_D1 DISP_DAT09 21 22 Reserved DISP_DAT10 23 C 24 DISP_DAT0 DISP_DAT11 25 N 26 DISP_DAT1 DISP_DAT12 27 1 28 DISP_DAT2 POWER 29 30 DISP_DAT3 DISP_DAT13 31 32 DISP_DAT4 DISP_DAT14 33 C 34 DISP_DAT5 DISP_DAT15 35 N 36 V_BAT DISP_DAT16 37 1 38 DISP_DAT6 DISP_DAT17 39 40 DISP_DAT7 DISP_DAT18 41 42 DISP_DAT21 DISP_DAT19 43 C 44 DISP_DAT22 DISP_DAT20 45 N 46 DISP_DAT23 POWER 47 1 48 EN_DISP_3.3V DISP_CLK 49 50 Reserved DISP_HSYNC 51 52 Reserved DISP_VSYNC 53 C 54 Reserved DISP_DATE 55 N 56 Reserved DISP_PWM 57 1 58 Reserved Reserved 59 60 Reserved Reserved 61 62 GND DIO_14 63 C 64 MUX_AD_15 DIO_13 65 N 66 MUX_AD_14 DIO_12 67 1 68 MUX_AD_13 DIO_11 69 70 MUX_AD_12 DIO_10 71 72 MUX_AD_11 DIO_9 73 C 74 MUX_AD_10 GND 75 N 76 MUX_AD_9 DIO_8 77 1 78 MUX_AD_8 DIO_7 79 80 MUX_AD_7 DIO_6 81 82 MUX_AD_6 DIO_5 83 C 84 MUX_AD_5 DIO_4 85 N 86 MUX_AD_4 DIO_3 87 1 88 MUX_AD_3 DIO_2 89 90 MUX_AD_2 DIO_1 91 92 MUX_AD_1 DIO_0 93 C 94 MUX_AD_0 GND 95 N 96 BUS_ALE# BUS_WAIT# 97 1 98 BUS_DIR BUS_BHE# 99 100 BUS_CS#

Name Pin Pin Name ETH_RX+ 1 2 ETH_LEFT_LED ETH_RX- 3 C 4 ETH_RIGHT_LED ETH_CT 5 N 6 RED_LED# ETH_TX+ 7 2 8 GREEN_LED# ETH_TX- 9 10 Reserved ETH_CT 11 12 Reserved #TS_3.2V 13 C 14 Reserved GND 15 N 16 TOUCH_X0 Reserved 17 2 18 TOUCH_X1 Reserved 19 20 TOUCH_Y0 GND 21 22 TOUCH_Y1 Reserved 23 C 24 Reserved Reserved 25 N 26 Reserved Reserved 27 2 28 TWI_CLK HOST_USB_M 29 30 TWI_DAT HOST_USB_P 31 32 EN_232_TRANS #FPGA_1.2V 33 C 34 Reserved USB_OTG_D- 35 N 36 AUD_CLK USB_OTG_D+ 37 2 38 AUD_FRM #TS_3.2V 39 40 AUD_TXD Reserved 41 42 AUD_RXD Reserved 43 C 44 CPU_JTAG_TMS GND 45 N 46 CPU_JTAG_TCK Reserved 47 2 48 CPU_JTAG_TDI Reserved 49 50 CPU_JTAG_TDO GND 51 52 ONE_WIRE Reserved 53 C 54 DIO_20 Reserved 55 N 56 GPIO1_7 DDR_1.8V 57 2 58 GPIO1_3 Reserved 59 60 GPIO1_5 Reserved 61 62 DIO_19 #2.775V_BOOT 63 C 64 DIO_18 SPI_CS# 65 N 66 GPIO4_13 SPI_MOSI 67 2 68 GPIO4_14 SPI_MISO 69 70 DIO_17 SPI_CLK 71 72 GPIO1_6 GND 73 C 74 USB_OTG_ID Reserved 75 N 76 USB_5V_LINE Reserved 77 2 78 UART0_TXD CPU_JTAG_VCC 79 80 UART0_RXD Reserved 81 82 UART1_TXD Reserved 83 C 84 UART1_RXD Reserved 85 N 86 UART2_TXD Reserved 87 2 88 UART2_RXD MFP_52 89 90 UART3_TXD DIAG_LED# 91 92 UART3_RXD DEBUG_TXD 93 C 94 UART4_TXD DEBUG_RXD 95 N 96 UART4_RXD DIO_47/CAN_TXD 97 2 98 UART5_TXD DIO_46/CAN_RXD 99 100 UART5_RXD