TS-9370 GPIO

From embeddedTS Manuals
Note: This section is incomplete at this time.

The i.MX93 CPU and FPGA GPIOs are exposed using a kernel character device. This interface provides a set of files and directories for interacting with GPIO which can be used from any language that interact with special files in linux using ioctl() or similar. For our platforms, we pre-install the "libgpiod" library and binaries. Documentation on these tools can be found here. This section only covers using these userspace tools and does not provide guidance on using the libgpiod library in end applications. Please see the libgpiod documentation for this purpose.

A user with suitable permissions to read and write /dev/gpiochip* files can immediately interact with GPIO pins. For example, to see if input power has failed: 

gpioget $(gpiofind POWER_FAIL_3V)

Multiple pins in the same chip can be read simultaneously by passing multiple pin numbers separated by spaces.

To write to a pin, the gpioset command is used. For example, to set Relay 1: 

gpioset $(gpiofind EN_RELAY_1)=1

Multiple pins in the same chip can be set simultaneously by passing multiple pin=value pairs separated by spaces.

If a call with gpioset or gpioget fails with "Device or resource busy," that means that specific GPIO is claimed by another device. The command cat /sys/kernel/debug/gpio can be used to get a list of all of the system GPIO and what has claimed them.

The gpiomon tool can be used to monitor pins for changes to GPIOs that generate interrupts (i.e., CPU GPIOs).

In the following table, gpiochips 0, 3 and 4 are on the CPU, and gpiochips 5 through 7 are on the FPGA. Because this numbering is subject to change, it is advisable to use the gpiofind command to look it up by its label, as shown in the usage examples above and elsewhere in this manual.

Schematic Net Name Chip Bank Line Location
EN_GREEN_LED_N FPGA 0 0
EN_YEL_LED_N FPGA 0 1
EN_RED_LED_N FPGA 0 2
NIM_RESET_N FPGA 0 4
NIM_CTS_N FPGA 0 5
NIM_PWR_ON_N FPGA 0 6
EN_NIM_USB_N FPGA 0 7
EN_NIM_4V FPGA 0 8
EN_NIM_3P3V FPGA 0 9
NIM_TXD FPGA 0 10
NIM_RXD FPGA 0 11
EN_USB_HOST1_VBUS FPGA 0 12
EN_USB_HOST2_VBUS FPGA 0 13
MIKRO_TXD FPGA 0 14
MIKRO_RXD FPGA 0 15
MIKRO_SPI_CLK FPGA 0 16
MIKRO_SPI_CS_N FPGA 0 17
MIKRO_SPI_MISO FPGA 0 18
MIKRO_SPI_MOSI FPGA 0 19
MIKRO_RESET_N FPGA 0 20
MIKRO_AN FPGA 0 21
MIKRO_PWM FPGA 0 22
MIKRO_INT FPGA 0 23
EN_LS_OUT_1 FPGA 0 24
EN_LS_OUT_2 FPGA 0 25
EN_LS_OUT_3 FPGA 0 26
EN_LS_OUT_4 FPGA 0 27
EN_HS_SW FPGA 0 28
DIO_FAULT_N FPGA 0 29
MAGNET_IRQ[1] FPGA 0 30
GYRO_IRQ[1] FPGA 0 31
PUSH_SW_PADN FPGA 1 22
AN_SEL_0 FPGA 1 23
AN_SEL_1 FPGA 1 24
EN_CL_1_2 FPGA 1 25
EN_CL_3 FPGA 1 26
DP_RESET_PADN FPGA 1 27
NO_SCAP_CHRG_PADN FPGA 1 28
EN_SPKR_AMP FPGA 1 29
BT_EN FPGA 1 30
WIFI_EN FPGA 1 31
EN_ADC_3_12V FPGA 2 0
EN_ADC_1_2_12V FPGA 2 1
Label Chip Block Pin Location
AN_CH4[1] CPU 0 0 AIN 4 or Digital Input AIN 4 on CN32 Terminal
RTC_BATT_FAIL CPU 0 1 Battery failed/missing on the Battery Connector
AN_CH0[1] CPU 0 4 AIN 0 on CN32 Terminal
AN_CH1[1] CPU 0 5 AIN 1 or Digital Input AIN 1 on CN32 Terminal
AN_CH2[1] CPU 0 8 AIN 2 or Digital Input AIN 2 on CN32 Terminal
AN_CH3[1] CPU 0 9 AIN 3 or Digital Input AIN 3 on CN32 Terminal
CPU 0 18 CPU Board Red LED
CPU 0 19 CPU Board Green LED
NIM_STATUS CPU 3 14 Pin 13 on CN16 (XBee/Nimbelink_Socket)
POWER_FAIL_3V CPU 4 0 Power Input Failure
FPGA_IRQ[1] CPU 4 1 FPGA Interrupt input pin
EN_RELAY_1 CPU 4 4 Relay 1 on CN32 Terminal
EN_RELAY_2 CPU 4 5 Relay 2 on CN32 Terminal
NIM_RESET CPU 4 6 Pin 5 on CN16 (XBee/Nimbelink_Socket)
DIO_1_OUT FPGA 5 0 DIO 1 Out or PWM on CN32 Terminal
DIO_2_OUT FPGA 5 1 DIO 2 Out or PWM on CN32 Terminal
DIO_1_IN FPGA 5 2 DIO 1 In on CN32 Terminal
DIO_2_IN FPGA 5 3 DIO 2 In on CN32 Terminal
DIO_3_IN FPGA 5 4 DIO 3 In on CN32 Terminal
DIO_6 FPGA 5 5 FPGA DIO 06
DIG_IN_1 FPGA 5 6 Digital In 1 on CN32 Terminal
DIG_IN_2 FPGA 5 7 Digital In 2 on CN32 Terminal
DIG_IN_3 FPGA 5 8 Digital In 3 on CN32 Terminal
EN_CL_1 FPGA 5 9 AIN 1 4-20 mA current loop enable
EN_CL_2 FPGA 5 10 AIN 2 4-20 mA current loop enable
EN_CL_3 FPGA 5 11 AIN 3 4-20 mA current loop enable
FPGA 5 12 Reserved
FPGA 5 13 Reserved
EN_CL_4 FPGA 5 14 AIN 4 4-20 mA current loop enable
EN_HS_SW FPGA 5 15 High-Side Switch or HSPWM
EN_ADC1_12V FPGA 6 1 AIN 1 0-12 V meas. mode [2]
EN_ADC2_12V FPGA 6 2 AIN 2 0-12 V meas. mode [2]
EN_ADC3_12V FPGA 6 3 AIN 3 0-12 V meas. mode [2]
EN_ADC4_12V FPGA 6 4 AIN 4 0-12 V meas. mode [2]
EN_USB_HOST_5V FPGA 6 5 en usb host 5v
PHY_RESET#[1] FPGA 6 6 Ethernet PHY reset
WIFI_RESET#[1] FPGA 6 7 WiFi module reset
IO_RED_LED#[1] FPGA 6 8 I/O Board Red LED
IO_GREEN_LED#[1] FPGA 6 9 I/O Board Green LED
FPGA 6 12 Reserved
DIO_3_OUT FPGA 6 13 DIO 3 Out or PWM on CN32 Terminal
EN_HSPWM FPGA 6 14 Enable high-side PWM
EN_LSPWM FPGA 6 15 Low-side PWM drain enable
CPU_TOUCH_IRQ#[1] FPGA 7 0 Touchscreen IRQ
FPGA 7 2 FPGA Strapping Pin
FPGA 7 3 FPGA Strapping Pin
FPGA 7 4 FPGA Strapping Pin
FPGA 7 5 FPGA Strapping Pin
NIM_3V3#_4V FPGA 7 6 Data 0: Select 3.3 V power on CN16 XBee Socket [3]
Data 1: Select 4 V power on CN16 XBee Socket [3]
NIM_PWR_ON FPGA 7 8 Pin 20 (Power Button) on CN16 XBee Socket
SEL_NIM_USB FPGA 7 9 Enable USB interface on CN16 XBee Socket [4]
DIO_FAULT# FPGA 7 10 I/O over-current/over-voltage breaker tripped [5]
FPGA 7 11 FPGA Strapping Pin
FPGA 7 12 FPGA Strapping Pin
FPGA 7 13 Reserved
EN_BK_LT#[1] FPGA 7 14 LCD backlight enable
  1. ↑ 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 Claimed by driver. Not available for use.
  2. ↑ 2.0 2.1 2.2 2.3 This bit is read only. Clearing the associated current loop enable bit will set this bit, setting the CL enable will clear this bit
  3. ↑ 3.0 3.1 To disable power on this pin, set the GPIO as an input with 'gpioset' or otherwise
  4. ↑ This will relocate the USB channel connected to the top USB host port
  5. ↑ This bit must be cleared manually after a trip to de-assert the associated IRQ


Digital Inputs

The digital inputs on the TS-7100-Z are capable of supporting various voltage ranges and input modes. The digital inputs support dry contact switches as well as a driven input voltage. The table below lists each digital input, the bank and pin number for reading the input, the maximum input voltage range, the threshold voltages, as well as the location of the input. VIH Min is the minimum voltage on the input to trigger a logic 1 input. VIL Max is the maximum voltage on the input to trigger a logic 0 input. All of the digital inputs are hysteretic. The driving input must be able to at least sink current to drive the input low, but all digital inputs are compatible with push-pull drivers.

Input Name Chip Bank Pin V Range VIH Min VIL Max Location
Digital In 1 FPGA 5 6 0-30 V ~2.57 V ~0.95 V CN32 Terminal, pin 9
Digital In 2 FPGA 5 7 0-30 V ~2.57 V ~0.95 V CN32 Terminal, pin 11
Digital In 3 FPGA 5 8 0-30 V ~2.57 V ~0.95 V CN32 Terminal, pin 13
DIO 1 In [1] FPGA 5 2 0-30 V ~2.54 V ~0.90 V CN32 Terminal, pin 14
DIO 2 In [1] FPGA 5 3 0-30 V ~2.54 V ~0.90 V CN32 Terminal, pin 16
DIO 3 In [1] FPGA 5 4 0-30 V ~2.54 V ~0.90 V CN32 Terminal, pin 18
AIN 1 In [2] CPU 0 5 0-12 V ~8.60 V ~7.90 V CN32 Terminal, pin 25
AIN 2 In [2] CPU 0 8 0-12 V ~8.60 V ~7.90 V CN32 Terminal, pin 23
AIN 3 In [2] CPU 0 9 0-12 V ~8.60 V ~7.90 V CN32 Terminal, pin 21
AIN 4 In [2] CPU 0 0 0-12 V ~8.60 V ~7.90 V CN32 Terminal, pin 19
  1. ↑ 1.0 1.1 1.2 This GPIO should only be read as an input. Its value reflects the voltage on the physical CN32 pin, regardless of output status
  2. ↑ 2.0 2.1 2.2 2.3 The AIN pins can be used as Digital Inputs, but require software changes first. See the ADC section for more information

Digital Outputs

The TS-7100-Z supports a handful of digital output pins. These are able to act as high-current low-side switches. The table below lists each digital output, the bank and pin number for accessing it, the maximum voltage rating, the maximum current output, as well as the location of the pin.

DIO Name Chip Bank Pin Max V Rating Max A Rating Location
DIO_1_OUT FPGA 5 0 30 V 700 mA (sink) [1] CN32 Terminal, pin 14
DIO_2_OUT FPGA 5 1 30 V 700 mA (sink) [1] CN32 Terminal, pin 16
DIO_3_OUT FPGA 6 13 30 V 700 mA (sink) [1] CN32 Terminal, pin 18
EN_HS_SW FPGA 5 15 48 V [2] 300 mA (source) [3] CN32 Terminal, pin 27
  1. ↑ 1.0 1.1 1.2 Not to exceed 1000 mA total across all three Digital I/O, doing so will cause the over-current breaker to trip
  2. ↑ The output voltage is the same as the TS-7100-Z input voltage
  3. ↑ Exceeding 330 mA will cause the over-current breaker to trip


Digital Output Over-Current Breaker

The TS-7100-Z I/O PCB in combination with the FPGA on the TS-7100, implements an electronic over-current breaker. When this breaker is tripped all three DIO Out paths will be disabled, the High-Side Switch output will be disabled, analog current loops will be disabled, and the red LED on the TS-7100-Z I/O board will be illuminated. That is, digital outputs will cease to sink or source any amount of current, and the AIN inputs will have 4-20 mA input disabled. The tripped breaker will also trigger a DIO fault breaker interrupt as well as set the associated GPIO flag DIO_FAULT#. The GPIO output DIO_FAULT# must be cleared manually in order to reset the IRQ output. However, once the breaker trips, and the trip condition is cleared; all relevant GPIO settings can immediately be re-enabled without clearing this GPIO output bit.


Trip Conditions

See the table above for each DIO channel's maximum current rating. Note that the breaker does NOT enforce these ratings per DIO channel. The breaker will trip if the combined total amount of current sunk from all three digital outputs exceeds 1 A.

See the table above for the High-Side Switch's maximum current rating. If the rated max supply current is exceeded, the breaker will trip.

Note that all of these are in parallel. If the combined DIO sink current OR High-Side Switch current is exceeded, then the breaker will trip. The over-current breaker will also disable analog 4-20 mA current loop measurements.

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