4500 TS-Socket

From embeddedTS Manuals
CN1 CN2
Name Pin Pin Name
FPGA_JTAG_TMS [1] 1 2 #EXT_RESET [2]
FPGA_JTAG_TCK [1] 3 C 4 DIO_07 [3]
FPGA_JTAG_TDO [1] 5 N 6 SDCARD_D2 [4]
FPGA_JTAG_TDI [1] 7 1 8 SDCARD_D3 [4]
OFF_BD_RESET# [5] 9 10 SDCARD_CMD [4]
Reserved 11 12 SDCARD_3.3V [4]
Reserved 13 C 14 SDCARD_CLK [4]
POWER [6] 15 N 16 POWER [6]
Reserved 17 1 18 SDCARD_D0 [4]
Reserved 19 20 SDCARD_D1 [4]
Reserved 21 22 Reserved
Reserved 23 C 24 Reserved
Reserved 25 N 26 Reserved
Reserved 27 1 28 Reserved
POWER [6] 29 30 Reserved
Reserved 31 32 Reserved
Reserved 33 C 34 Reserved
Reserved 35 N 36 V_BAT [7]
Reserved 37 1 38 Reserved
Reserved 39 40 Reserved
Reserved 41 42 Reserved
Reserved 43 C 44 Reserved
Reserved 45 N 46 Reserved
POWER [6] 47 1 48 Reserved
Reserved 49 50 Reserved
Reserved 51 52 Reserved
Reserved 53 C 54 Reserved
Reserved 55 N 56 Reserved
Reserved 57 1 58 Reserved
Reserved 59 60 Reserved
Reserved 61 62 Ground
DIO_14 63 C 64 DIO_34 / AD_15
DIO_13 65 N 66 DIO_33 / AD_14
DIO_12 67 1 68 DIO_32 / AD_13
DIO_11 69 70 DIO_31 / AD_12
DIO_10 71 72 DIO_30 / AD_11
DIO_09 73 C 74 DIO_29 / AD_10
Ground 75 N 76 DIO_28 / AD_09
DIO_08 77 1 78 DIO_27 / AD_08
DIO_07 79 80 NAND_D7 / AD_07
DIO_06 81 82 NAND_D6 / AD_06
DIO_05 83 C 84 NAND_D5 / AD_05
DIO_04 85 N 86 NAND_D4 / AD_04
DIO_03 87 1 88 NAND_D3 / AD_03
DIO_02 89 90 NAND_D2 / AD_02
DIO_01 91 92 NAND_D1 / AD_01
DIO_00 93 C 94 NAND_D0 / AD_00
Ground 95 N 96 DIO_26 / BUS_ALE#
Reserved 97 1 98 DIO_25 / BUS_DIR
DIO_23 / BUS_BHE# 99 100 DIO_24 / BUS_CS#
Name Pin Pin Name
ETH_RX+ 1 2 ETH_LEFT_LED
ETH_RX- 3 C 4 ETH_RIGHT_LED
ETH_CT 5 N 6 RED_LED#
ETH_TX+ 7 2 8 GREEN_LED#
ETH_TX- 9 10 Reserved
ETH_CT 11 12 Reserved
3.3V [8] 13 C 14 Reserved
Ground 15 N 16 Reserved
Reserved 17 2 18 Reserved
Reserved 19 20 Reserved
Ground 21 22 Reserved
DEV_USB_M 23 C 24 Reserved
DEV_USB_P 25 N 26 Reserved
Ground 27 2 28 TWI_CLK
HOST_USB_M 29 30 TWI_DAT
HOST_USB_P 31 32 Reserved
CPU_CORE 33 C 34 Reserved
HOSTB_USB_M 35 N 36 Reserved
HOSTB_USB_P 37 2 38 Reserved
3.3V [8] 39 40 Reserved
Reserved 41 42 Reserved
Reserved 43 C 44 CPU_JTAG_TMS
Ground 45 N 46 CPU_JTAG_TCK
Reserved 47 2 48 CPU_JTAG_TDI
Reserved 49 50 CPU_JTAG_TDO
Ground 51 52 Reserved
Reserved 53 C 54 DIO_50
Reserved 55 N 56 DIO_51
1.8V 57 2 58 DIO_52
Reserved 59 60 DIO_43
Reserved 61 62 DIO_49
1.2V 63 C 64 DIO_17
DIO_48 65 N 66 DIO_18
SPI_MOSI 67 2 68 DIO_19
SPI_MISO 69 70 DIO_20
SPI_CLK 71 72 DIO_21
Ground 73 C 74 Reserved
Reserved 75 N 76 Reserved
Reserved 77 2 78 DIO_36 / XUART0_TXD
3.3V [8] 79 80 DIO_37 / UART0_RXD
Reserved 81 82 DIO_38 / UART1_TXD
Reserved 83 C 84 DIO_39 / UART1_RXD
Reserved 85 N 86 DIO_22 / UART2_TXD
Reserved 87 2 88 DIO_44 / UART2_RXD
Reserved 89 90 DIO_45 / UART3_TXD
Reserved 91 92 DIO_46 / UART3_RXD
DEBUG_TXD 93 C 94 DIO_47 / UART4_TXD
DEBUG_RXD 95 N 96 DIO_40 / UART4_RXD
DIO_15 / CAN_TXD 97 2 98 DIO_41 / UART5_TXD
DIO_16 / CAN_RXD 99 100 DIO_42 / UART5_RXD
  1. ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported. See the #FPGA Programming section for the recommended method to reprogram the FPGA.
  2. ↑ EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
  3. ↑ On our baseboard designs this pin is typically used to toggle power to the USB 5V rail (EN_USB_5V).
  4. ↑ 4.0 4.1 4.2 4.3 4.4 4.5 4.6 For more information on working with SD cards see the #SD section. These pins for the SD controller are also the same pins brought out on the MicroSD socket so they cannot both be used at the same time.
  5. ↑ The off board reset is driven low to reset all peripherals.
  6. ↑ 6.0 6.1 6.2 6.3 Each pin on this connector is only rated for 500mA so every POWER pin should be connected to a 5V source.
  7. ↑ Optionally you can connect a 3.3V battery to this pin to keep the RTC alive between reboots and while the 5V rail is down.
  8. ↑ 8.0 8.1 8.2 The System-on-Module regulates a 3.3V rail which can source up to 300mA by the baseboard.
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