47xx EVGPIO
This board features the EVGPIO core (Event Driven GPIO) which allows a low bandwidth mechanism to monitor all FPGA DIO on a shared interrupt. All DIO are accessed atomically through two registers. The data register is used to read dio state changes, set output values, and data direction. The mask register is used to set which DIO will trigger the IRQ and provide state changes to the data register. We provide "evgpioctl" which can be used to access these DIO:
# evgpioctl --help
Usage: evgpioctl [OPTIONS] ...
EVGPIO utility
-i, --getin <dio> Returns the input value of a DIO
-s, --setout <dio> Sets a DIO output value high
-l, --clrout <dio> Sets a DIO output value low
-o, --ddrout <dio> Set DIO to an output
-d, --ddrin <dio> Set DIO to an input
-m, --setmask <dio> Mask out a DIO so it does not provide input
event changes and trigger the shared IRQ
-c, --clrmask <dio> Clear the mask from a DIO so it provides input
event changes and trigger the shared IRQ
-w, --watch Prints csv output when any unmasked DIO changes
<dio>,<1=high,0=low>
This provides a simple interface that can be used in scripts, or wrapped for higher level software access.
# Set DIO 31 to a high output
evgpioctl --ddrout 31 --setout 31
# Set DIO 31 to a low output
evgpioctl --setout 31
# Read the value of DIO 30
evgpioctl --ddrin 30 --getin 30
# The input return values are parsable and can be used easily in scripts:
eval $(evgpioctl --getin 30)
echo $dio30
The sources for this utility are available here:
You can also manipulate the EVGPIO data and mask registers directly in your application. Setting a pin direction, output value, and reading input changes are accessed through the EVPGIO data register.
| Bits | Description |
|---|---|
| 15:9 | Reserved (Write 0) |
| 8 | Valid Read Data [1] |
| 7 | Value |
| 6 | Data/Data Direction [2] |
| 5:0 | DIO number |
- ↑ When writing, write 0. During a read this indicates if this read includes new valid changes. After an interrupt this register should be read until it returns 0.
- ↑ When bit6 = 0, data direction of DIO is set to value (bit7 1 = output, 0 = input). When bit6 = 1, the data output of DIO is set to value
The second register is the IRQ mask. This is used to set which DIO will update the data register and trigger an IRQ on change.
| Bits | Description |
|---|---|
| 15:8 | Reserved (Write 0) |
| 7 | Mask Set (0 = irq enabled, 1 = irq disabled) |
| 6 | Reserved (Write 0) |
| 5:0 | DIO number |