75XX Syscon

The Syscon is an FPGA core that presents various configuration registers for the board. These registers are accessed through the SBUS. For example, to read the "Model ID" register:

ts7500ctl --address=0x60 --peek16

See the SBUS page for more details on using the SBUS in your application.

Offset	Bits	Access	Function
0x60	15-0	Read Only	Model ID
0x62	15	Read/Write	Green LED (1 = on)
	14	Read/Write	Red LED (1 = on)
	13	Read/Write	RTC SCL input
	12	Read/Write	RTC SDA input
	11	Read/Write	RTC SCL direction (1 - output)
	10	Read/Write	RTC SDA direction (1 - output)
	9	Read/Write	RTC SCL output
	8	Read/Write	RTC SDA output
	7-4	Read Only	Board submodel
	3-0	Read Only	FPGA revision
0x64	15-0	Read Only	16-bits of random data changed every 1 second.
0x66	15-12	Read Only	DIO input for pins 40(MSB)-37(LSB)
	11-8	Read/Write	DIO output for pins 40(MSB)-37(LSB)
	7-4	Read/Write	DIO direction for pins 40(MSB)-37(LSB) (1 - output)
	3	Read/Write	Lattice tagmem clock
	2	Read/Write	Lattice tagmem serial-in (RW)
	1	Read/Write	Lattice tagmem CSn
	0	Read Only	Lattice tagmem serial-out (RO)
0x68	15-0	Read Only	DIO input for pins 36(MSB)-21(LSB)
0x6a	15-0	Read Only	DIO output for pins 36(MSB)-21(LSB)
0x6c	15-0	Read/Write	DIO direction for pins 36(MSB)-21(LSB) (1 - output)
0x6e	15-0	Read/Write	DIO input for pins 20(MSB)-5(LSB)
0x70	15-0	Read/Write	DIO output for pins 20(MSB)-5(LSB)
0x72	15-0	Read/Write	DIO direction for pins 20(MSB)-5(LSB) (1 - output)
0x74	15-0	Write Only	#Watchdog feed register
0x76	15-11	N/A	Reserved
	10-6	Read/Write	PLL phase (set by TS-BOOTROM)
	5	Read Only	mode3 latched bootstrap bit
	4	Read/Write	Reset switch enable (1 - auto reboot when dio_i[9] == 0)
	3-2	Read/Write	scratch reg
	1	Read Only	mode2 latched bootstrap bit
	0	Read Only	mode1 latched bootstrap bit