TS-4100-iospecs
From embeddedTS Manuals
The GPIO external to the TS-4100 are all nominally 3.3 V, but will have differences depending on if they are CPU/FPGA pins.
The CPU pins have adjustable drive strength and pull resistor configuration. These can be adjusted in software and will have initial values in the device tree. See the device tree for information and details about specific I/O.
The FPGA I/O cannot be adjusted further in software.
| IO | Typical Range | Absolute Range | Logic Low Max. Input | Logic High Min. Input | Drive Strength |
|---|---|---|---|---|---|
| External CPU GPIO | 0 V to 3.3 VDC | -0.5 V to 3.6 V | 0.99 V | 2.31 V | 50 mA |
| External FPGA GPIO | 0 V to 3.3 VDC | -0.5 V to 3.75 V | 0.8 V | 2.0 V | 8 mA |
Refer to the MachXO2 Family Datasheet for more detail on the FPGA I/O. Refer to the CPU datasheet for further details on the CPU I/O.
| Note: | Do not drive any I/O externally until the 3.3 V rail is valid. Doing so can violate the power sequencing causing boot failures or damage to the device. |