TS-4500 Syscon
From embeddedTS Manuals
The Syscon is an FPGA core that presents various configuration registers for the board. These registers are accessed through the SBUS. For example, to read the "Model ID" register:
ts7500ctl --address=0x60 --peek16
Most of these functions are already implemented in ts7500ctl which can be used as a reference implementation.
Offset | Bits | Access | Function |
---|---|---|---|
0x60 | 15-0 | Read Only | Model ID |
0x62 | 15 | Read/Write | Green LED (1 = on) |
14 | Read/Write | Red LED (1 = on) | |
13 | Read/Write | RTC SCL input | |
12 | Read/Write | RTC SDA input | |
11 | Read/Write | RTC SCL direction (1 - output) | |
10 | Read/Write | RTC SDA direction (1 - output) | |
9 | Read/Write | RTC SCL output | |
8 | Read/Write | RTC SDA output | |
7-4 | Read Only | Board submodel | |
3-0 | Read Only | FPGA revision [1] | |
0x64 | 15-0 | Read Only | 16-bits of random data changed every 1 second. |
0x66 | 15-12 | Read Only | DIO input for pins 40(MSB)-37(LSB) |
11-8 | Read/Write | DIO output for pins 40(MSB)-37(LSB) | |
7-4 | Read/Write | DIO direction for pins 40(MSB)-37(LSB) (1 - output) | |
3 | Read/Write | Lattice tagmem clock | |
2 | Read/Write | Lattice tagmem serial-in (RW) | |
1 | Read/Write | Lattice tagmem CSn | |
0 | Read Only | Lattice tagmem serial-out (RO) | |
0x68 | 15-0 | Read Only | DIO input for pins 36(MSB)-21(LSB) |
0x6a | 15-0 | Read Only | DIO output for pins 36(MSB)-21(LSB) |
0x6c | 15-0 | Read/Write | DIO direction for pins 36(MSB)-21(LSB) (1 - output) |
0x6e | 15-0 | Read/Write | DIO input for pins 20(MSB)-5(LSB) |
0x70 | 15-0 | Read/Write | DIO output for pins 20(MSB)-5(LSB) |
0x72 | 15-0 | Read/Write | DIO direction for pins 20(MSB)-5(LSB) (1 - output) |
0x74 | 15-0 | Write Only | Watchdog feed register |
0x76 | 15-14 | N/A | Reserved |
13 | Read/Write | RS422 enable [2] | |
12 | Read/Write | TS-8510 RS422 enable [2] | |
11 | Read/Write | CAN Enable | |
10-6 | Read/Write | PLL phase | |
5 | Read Only | mode3 latched bootstrap bit | |
4 | Read/Write | Reset switch enable (1 - auto reboot when dio_i[9] == 0) | |
3-2 | Read/Write | scratch reg | |
1 | Read Only | mode2 latched bootstrap bit | |
0 | Read Only | mode1 latched bootstrap bit | |
0x78 | 15 | Read Only | Reserved |
14-10 | Read Only | DIO Input for pins 4(MSB)-0(LSB) | |
9-5 | Read/Write | DIO output for pins 4(MSB)-0(LSB) | |
4-0 | Read/Write | DIO direction for pins 4(MSB)-0(LSB) | |
0x7a | 15-8 | Read/Write | DIO output for pins 48(MSB)-41(LSB) |
7-0 | Read/Write | DIO direction for pins 48(MSB)-41(LSB) | |
0x7c | 15-12 | Read Only | Reserved |
11-0 | Read Only | DIO input for pins 52(MSB)-41(LSB) | |
0x7e | 15-8 | Read Only | Reserved |
7-4 | Read/Write | DIO output for pints 52(MSB)-49(LSB) | |
3-0 | Read/Write | DIO direction for pins 52(MSB)-49(LSB) |
- ↑ See #FPGA Bitstreams for more information on the FPGA revisions.
- ↑ 2.0 2.1 See the #COM Ports section for more details about this register