TS-4600 DIO

This board uses both CPU and a DIO controller in the FPGA. The CPU DIO typically have up to 4 functions associated with various pins (I2C, PWM, SPI, etc). See the CPU manual CPU manual for the complete listing and for information on how to control these DIO. This section only lists FPGA DIO.
Bit masking: Any bits not expressly mentioned here should be masked out. Direction setting: 0 is input, 1 is output.

All FPGA DIO are controlled by three distinct register types: Direction, Input Data, and Output Data. To use any DIO pin, the direction register must be set (0 for input, 1 for output), then either the input register may be read, or the output register may be written to. These registers are described in the Syscon memory table.
For example, to write to DIO_0, bit 0 (the LSB) of 0xC (The direction register for DIO_0 through DIO_15) must be set high, then the desired value (high = 1 low = 0) should be written to bit 0 of 0xA (the Output Data register for DIO_0 through DIO_15). Alternatively to read the status of that pin, the Direction Register must be set low, then bit zero of 0x8 would reflect the status of that pin.

The TS-4600 FPGA contains our EVGPIO core, event driven GPIO. This allows for atomic setting of DIO pins (no need to read-modify-write) as well as setting up pins to generate interrupts on state changes. See the EVGPIO and Interrupts sections for more information.
All 69 of the DIO from the FPGA will default to the DIO mode. These pins coming from the FPGA are all 3.3V tolerant. To manipulate these DIO you can access the Syscon, either through tshwctl or a custom application.

DIO Number	Connector Location	Alternate Function
0	CN1_93	N/A
1	CN1_91	N/A
2	CN1_89	N/A
3	CN1_87	12.5MHz/14.28MHz clock
4	CN1_85	N/A
5	CN1_83	Board ID
6	CN1_81	ADC_DAT
7	CN1_79	XUART5 TX_EN, ADC_CLK
8	CN1_77	AN_SEL, XUART1 TX_EN
9	CN1_73	External Reset
10	CN1_71	XUART2 TX_EN
11	CN1_69	N/A
12	CN1_67	XUART0 TX_EN
13	CN1_65	XUART3 TX_EN
14	CN1_63	XUART4 TX_EN
15	CN2_97	CAN1_TXD
16	CN2_99	CAN1_RXD
17	CN1_97	BUS_WAIT#
18	CN1_99	BUS_BHE#
19	CN1_100	BUS_CS#
20	CN1_98	BUS_DIR, MODE2
21	CN1_96	BUS_ALE#
22	CN1_94	MUX_AD_00
23	CN1_92	MUX_AD_01
24	CN1_90	MUX_AD_02
25	CN1_88	MUX_AD_03
26	CN1_86	MUX_AD_04
27	CN1_84	MUX_AD_05
28	CN1_82	MUX_AD_06
29	CN1_80	MUX_AD_07
30	CN1_78	MUX_AD_08
31	CN1_76	MUX_AD_09
32	CN1_74	MUX_AD_10
33	CN1_72	MUX_AD_11
34	CN1_70	MUX_AD_12
35	CN1_68	MUX_AD_13
36	CN1_66	MUX_AD_14
37	CN1_64	MUX_AD_15
38	CN2_72	N/A
39	CN2_70	N/S
40	CN2_68	N/A
41	CN2_66	XUART0 CTS
42	CN2_64	XUART1 CTS
43	CN2_62	XUART2 CTS
44	CN2_60	XUART3 CTS
45	CN2_58	XUART4 CTS
46	CN2_56	XUART5 CTS
47	CN2_52	N/A
48	CN2_32	N/A
49	CN1_61	N/A
50	CN1_59	N/A
51	CN1_60	N/A
52	CN1_58	N/A
53	CN2_78	XUART0 TXD
54	CN2_80	XUART0 RXD
55	CN2_82	XUART1 TXD
56	CN2_84	XUART1 RXD
57	CN2_86	XUART2 TXD
58	CN2_88	XUART2 RXD
59	CN2_90	XUART3 TXD
60	CN2_92	XUART3 RXD
61	CN2_94	XUART4 TXD
62	CN2_96	XUART4 RXD
63	CN2_98	XUART5 TXD
64	CN2_100	XUART5 RXD
65	CN2_67	SPI_MOSI
66	CN2_71	SPI_CLK
67	CN2_69	SPI_MISO
68	CN2_65	SPI_FRM
69	CN1_4	N/A