TS-4600 FPGA
From embeddedTS Manuals
This board features a Lattice LFXP2 FPGA. The CPU connects to the FPGA using a parallel bus implemented with the i.MX28 GPIO, and since access to this bus is not atomic we have implemented the NBUS as a safe way for multiple processes to access FPGA registers. All registers contained in the FPGA are 16bit wide, and there are 8bits of addressable registers. The following is a table of peripherals in the FPGA and their addresses:
| Offset | Usage |
|---|---|
| 0x00 | Syscon registers |
| 0x30 | ADC registers (for off-board ADC) |
| 0x40 | XUART IO registers |
| 0x58 | Touchscreen registers |
| 0x5c | Memwindow to 16KB blockram (for XUART buffer) |
| 0x60 | SPI interface |
| 0x70 | General memwindow registers |