TS-4800 Syscon
From embeddedTS Manuals
The registers listed below are all 16 bit registers and must be accessed with 16 bit reads and writes. This register block appears at base address 0xb0010000. You can use the peekpoke command as a simple way of manipulating these registers:
peekpoke 16 0xb0010000
This will return "0x4800" which matches the model ID register below.
| Offset | Bits | Access | Usage |
|---|---|---|---|
| 0x0 | 15:0 | Read Only | Model ID register. Reads 0x4800 on TS-4800 |
| 0x2 | 15 | Read/Write | Reset FPGA |
| 14 | Reserved (write 0) | ||
| 13 | SD Power (1 = on) | ||
| 12 | Boot mode | ||
| 11 | Baseboard 12MHz clk (overrides DIO 3) | ||
| 10 | Reserved | ||
| 9 | CAN1 IRQ enable | ||
| 8 | Reserved | ||
| 7:4 | Read Only | board submodel - 0x0 on production TS-4800 | |
| 3:0 | Read Only | FPGA revision | |
| 0x4 | 15:0 | Read Only | 32-bit 72MHz free running counter (16 LSBs) |
| 0x6 | 15:0 | Read Only | 32-bit 72MHz free running counter (16 MSBs) |
| 0x8 | 15:0 | Read Only | 32-bit 1MHz free running counter (16 LSBs) |
| 0xa | 15:0 | Read Only | 32-bit 1MHz free running counter (16 MSBs) |
| 0xc | 15:0 | Read Only | 16-bit random number |
| 0xe | 15:2 | Read Only | Reserved |
| 1:0 | Write Only | Watchdog feed register (write only) | |
| 0x10 | 15 | Read/Write | Green LED (1 = on) |
| 14 | Red LED (1 = on) | ||
| 13 | IRQ7 enable (1 = on) | ||
| 12 | IRQ6 enable (1 = on) | ||
| 11 | IRQ5 enable (1 = on) | ||
| 10 | Reserved | ||
| 9 | Sound Codec enable (1 = on) | ||
| 8 | Motor Controller enable (1 = on) | ||
| 7 | SPI enable (1 = on) | ||
| 6 | TOUCHSCREEN enable (1 = on) | ||
| 5 | XUART5 enable (1 = on) | ||
| 4 | XUART4 enable (1 = on) | ||
| 3 | XUART3 enable (1 = on) | ||
| 2 | XUART0 enable (1 = on) | ||
| 1 | CAN1 enable (1 = on) | ||
| 0 | CAN0 enable (1 = on) | ||
| 0x12 | 15:0 | Read/Write | MUXBUS configuration register |
| 0x14 | 15:4 | Read Only | Reserved |
| 3 | Read/Write | Lattice tagmem clock | |
| 2 | Read/Write | Lattice tagmem serial-in | |
| 1 | Read/Write | Lattice tagmem CSn | |
| 0 | Read Only | Lattice tagmem serial-out | |
| 0x16 | 15 | Read/Write | Input counter1 enable |
| 14 | Input counter0 enable | ||
| 13 | System-on-Module RS422 enable (xuart0 = DIO_13) | ||
| 12 | System-on-Module RS422 Enable (xuart4 = DIO_13) | ||
| 11 | Reserved | ||
| 10:6 | PLL phase (set by TS-BOOTROM) (RW) | ||
| 5 | Mode3 latched bootstrap bit (RO) | ||
| 4 | Reset switch enable (1 = auto reboot when dio_i[9] == 0) (RW) | ||
| 3:2 | Scratch Register (used by bootrom) | ||
| 1 | Mode2 latched bootstrap bit (RO) | ||
| 0 | Mode1 latched bootstrap bit (RO) | ||
| 0x1a | 15:0 | Read Only | Input counter0 |
| 0x1c | 15:0 | Read Only | Input counter1 |
| 0x1e | 15:0 | Read/Write | Test Register |
| 0x20 | 15:0 | Read Only | DIO input data for DIO 15(MSB)-0(LSB) |
| 0x22 | 15:0 | Read/Write | DIO output data for DIO 15(MSB)-0(LSB) |
| 0x24 | 15:0 | Read/Write | DIO direction for DIO 15(MSB)-0(LSB) (1 = output) |
| 0x28 | 15:0 | Read Only | DIO input data for DIO 31(MSB)-16(LSB) |
| 0x2a | 15:0 | Read/Write | DIO output data for DIO 31(MSB)-16(LSB) |
| 0x2c | 15:0 | Read/Write | DIO direction for DIO 31(MSB)-16(LSB) (1 = output) |
| 0x30 | 15:0 | Read Only | DIO input data for DIO 47(MSB)-32(LSB) |
| 0x32 | 15:0 | Read/Write | DIO output data for DIO 47(MSB)-32(LSB) |
| 0x34 | 15:0 | Read/Write | DIO direction for DIO 47(MSB)-32(LSB) (1 = output) |
| 0x38 | 15:8 | Read Only | Reserved |
| 7:0 | Read Only | DIO input data for DIO 55(MSB)-48(LSB) | |
| 0x3a | 15:8 | Read Only | Reserved |
| 7:0 | Read/Write | DIO output data for DIO 55(MSB)-48(LSB) | |
| 0x3c | 15:8 | Read/Write | Reserved |
| 7:0 | Read/Write | DIO direction for DIO 55(MSB)-48(LSB) (1 = output) |