TS-4900 DIO Table
From embeddedTS Manuals
The GPIO numbers in the table below are relevant to how the Linux references these numbers. The CPU documentation refers to bank and IO while Linux flattens this out to one number space.
CPU PAD [1] | GPIO Number | Common Functions [2] | Location |
---|---|---|---|
SD4_DAT1 | 41 | LCD_PWM[3], #GPIO | CN1_57 |
KEY_COL2 | 106 | CAN_1_TXD, #GPIO | CN2_97 |
KEY_ROW2 | 107 | CAN_1_RXD, #GPIO | CN2_99 |
KEY_COL0 | 102 | UART4_TXD | CN2_86, #FPGA Muxed |
KEY_ROW0 | 103 | UART4_RXD | CN2_88, #FPGA Muxed |
KEY_COL1 | 104 | UART5_TXD | CN2_90 |
KEY_ROW1 | 105 | UART5_RXD | CN2_92 |
KEY_COL3 | 108 | I2C_2_CLK | CN2_28 |
KEY_ROW3 | 109 | I2C_2_DAT | CN2_30 |
KEY_COL4 | 110 | CAN_2_TXD, #GPIO | CN1_71 |
KEY_ROW4 | 111 | CAN_2_RXD, #GPIO | CN1_69 |
GPIO_0 | 0 | AUD_MCLK | CN2_54 |
GPIO_1 | 1 | USB_OTG_ID | CN2_74 |
GPIO_2 | 2 | Red LED | Onboard |
CSI0_DAT17 [4] | 163 | #GPIO | CN2_56 |
SD4_DAT7 [5] | 47 | #GPIO | CN2_58 |
GPIO_7 | 7 | UART2_TXD | CN2_78, #FPGA Muxed |
GPIO_8 | 8 | UART2_RXD | CN2_80, #FPGA Muxed |
SD3_RST [6] | 200 | #GPIO | CN2_60 |
GPIO_16 | 203 | #GPIO | CN2_62 |
GPIO_17 | 204 | #GPIO | CN2_64 |
GPIO_19 | 101 | #GPIO | CN2_68 |
CSI0_MCLK | 147 | #GPIO | CN2_70 |
CSI0_PIXCLK | 146 | #GPIO | CN2_72 |
CSI0_DAT4 | 150 | AUD_CLK, #GPIO | CN2_36 |
CSI0_DAT5 | 151 | AUD_TXD, #GPIO | CN2_40 |
CSI0_DAT6 | 152 | AUD_FRM, #GPIO | CN2_38 |
CSI0_DAT7 | 153 | AUD_RXD, #GPIO | CN2_42 |
CSI0_DAT8 | 154 | SPI_2_CLK | CN2_71 |
CSI0_DAT9 | 155 | SPI_2_MOSI | CN2_67 |
CSI0_DAT10 | 156 | SPI_2_MISO | CN2_69 |
CSI0_DAT11 | 157 | SPI_2_CS# | CN2_65 |
CSI0_DAT12 | 158 | #GPIO | CN2_52 |
CSI0_DAT13 | 159 | #GPIO | CN2_66 |
DI0_DISP_CLK | 112 | LCD_CLK, #GPIO | CN1_49 |
DI0_PIN2 | 114 | LCD_HSYNC, #GPIO | CN1_51 |
DI0_PIN3 | 115 | LCD_VSYNC, #GPIO | CN1_53 |
DI0_PIN15 | 113 | LCD_DE, #GPIO | CN1_55 |
DISP0_DAT0 | 117 | LCD_D00, #GPIO | CN1_24 |
DISP0_DAT1 | 118 | LCD_D01, #GPIO | CN1_26 |
DISP0_DAT2 | 119 | LCD_D02, #GPIO | CN1_28 |
DISP0_DAT3 | 120 | LCD_D03, #GPIO | CN1_30 |
DISP0_DAT4 | 121 | LCD_D04, #GPIO | CN1_32 |
DISP0_DAT5 | 122 | LCD_D05, #GPIO | CN1_34 |
DISP0_DAT6 | 123 | LCD_D06, #GPIO | CN1_38 |
DISP0_DAT7 | 124 | LCD_D07, #GPIO | CN1_40 |
DISP0_DAT8 | 125 | LCD_D08, #GPIO | CN1_19 |
DISP0_DAT9 | 126 | LCD_D09, #GPIO | CN1_21 |
DISP0_DAT10 | 127 | LCD_D10, #GPIO | CN1_23 |
DISP0_DAT11 | 133 | LCD_D11, #GPIO | CN1_25 |
DISP0_DAT12 | 134 | LCD_D12, #GPIO | CN1_27 |
DISP0_DAT13 | 135 | LCD_D13, #GPIO | CN1_31 |
DISP0_DAT14 | 136 | LCD_D14, #GPIO | CN1_33 |
DISP0_DAT15 | 137 | LCD_D15, #GPIO | CN1_35 |
DISP0_DAT16 | 138 | LCD_D16, #GPIO | CN1_37 |
DISP0_DAT17 | 139 | LCD_D17, #GPIO | CN1_39 |
DISP0_DAT18 | 140 | LCD_D18, #GPIO | CN1_41 |
DISP0_DAT19 | 141 | LCD_D19, #GPIO | CN1_43 |
DISP0_DAT20 | 142 | LCD_D20, #GPIO | CN1_45 |
DISP0_DAT21 | 143 | LCD_D21, #GPIO | CN1_42 |
DISP0_DAT22 | 144 | LCD_D22, #GPIO | CN1_44 |
DISP0_DAT23 | 145 | LCD_D23, #GPIO | CN1_46 |
EIM_LBA | 59 | #GPIO, BUS_ALE# | CN1_96 |
EIM_OE | 57 | #GPIO [7] | CN1_83 |
EIM_RW | 58 | #GPIO,BUS_DIR | CN1_98 |
EIM_CS0 | 55 | #GPIO, BUS_CS# | CN1_100 |
EIM_CS1 | 56 | Green LED | Onboard |
EIM_A16 | 54 | #GPIO EN_USB_5V [8] | CN1_04 |
EIM_A17 | 53 | #GPIO OFF_BD_RESET# [9] | CN1_09 |
EIM_A18 | 52 | #GPIO | CN1_81 |
EIM_A19 | 51 | #GPIO EN_LCD_3.3V [10] | CN1_48 |
EIM_A20 | 50 | #GPIO | CN1_85 |
EIM_A21 | 49 | #GPIO | CN1_77 |
EIM_A22 | 48 | #GPIO | CN1_89 |
EIM_A23 | 166 | #GPIO | CN1_91 |
EIM_A24 | 132 | #GPIO [7] | CN1_93 |
EIM_D16 | 80 | SPI_1_CLK | CN1_60 |
EIM_D17 | 81 | SPI_1_MISO | CN1_56 |
EIM_D18 | 82 | SPI_1_MOSI | CN1_58 |
EIM_D19 | 83 | SPI_1_CS# [11] | Onboard |
EIM_D21 | 85 | I2C_1_CLK [12] | Onboard |
EIM_D28 | 92 | I2C_1_DAT [12] | Onboard |
EIM_D24 | 88 | UART3_TXD | CN2_82 |
EIM_D25 | 89 | UART3_RXD | CN2_84 |
EIM_EB1 | 61 | BUS_BHE#, #GPIO | CN1_99 |
EIM_BCLK | 191 | #GPIO | CN1_79 |
EIM_WAIT | 128 | BUS_WAIT#, #GPIO [7] | CN1_97 |
EIM_D31 | 95 | #GPIO | CN1_65 |
EIM_DA0 | 64 | MUX_AD_00, #GPIO | CN1_94 |
EIM_DA1 | 65 | MUX_AD_01, #GPIO | CN1_92 |
EIM_DA2 | 66 | MUX_AD_02, #GPIO | CN1_90 |
EIM_DA3 | 67 | MUX_AD_03, #GPIO | CN1_88 |
EIM_DA4 | 68 | MUX_AD_04, #GPIO | CN1_86 |
EIM_DA5 | 69 | MUX_AD_05, #GPIO | CN1_84 |
EIM_DA6 | 70 | MUX_AD_06, #GPIO | CN1_82 |
EIM_DA7 | 71 | MUX_AD_07, #GPIO | CN1_80 |
EIM_DA8 | 72 | MUX_AD_08, #GPIO | CN1_78 |
EIM_DA9 | 73 | MUX_AD_09, #GPIO | CN1_76 |
EIM_DA10 | 74 | MUX_AD_10, #GPIO | CN1_74 |
EIM_DA11 | 75 | MUX_AD_11, #GPIO | CN1_72 |
EIM_DA12 | 76 | MUX_AD_12, #GPIO | CN1_70 |
EIM_DA13 | 77 | MUX_AD_13, #GPIO | CN1_68 |
EIM_DA14 | 78 | MUX_AD_14, #GPIO | CN1_66 |
EIM_DA15 | 79 | MUX_AD_15, #GPIO | CN1_64 |
- ↑ The pad name does not often correspond with the functionality of the IO we use, but can be used to reference the pad in the CPU manual.
- ↑ This does not contain all of the functions possible for a pin, but the common functions as they are used on our off the shelf basebords. Consult the i.MX6 CPU Reference manual for a complete list.
- ↑ This pin is used to tune the LCD backlight through the PWM controller. On our baseboards where there is an LCD present this is connected to provide a sysfs tunable backlight. On other baseboards this is usable as a GPIO.
- ↑ This pin changed during the sampling program for the REV C boards. On rev A this was linux gpio #5, or pad "GPIO_5".
- ↑ This pin changed during the sampling program for the REV C boards. On rev A this was linux gpio #6, or pad "GPIO_6"
- ↑ This pin changed during the sampling program for the REV C boards. On rev A this was linux gpio #9, or pad "GPIO_9"
- ↑ 7.0 7.1 7.2 This GPIO stays LOW when power is applied and defaults to a low state until modified by software
- ↑ On our off the shelf baseboards this pin typically controls the 5V rail for USB peripherals. For custom designs this can optionally be connected to a FET to control USB peripherals power.
- ↑ This pin is dedicated to resetting offboard peripherals during a full reboot.
- ↑ On our off the shelf baseboards this is normally used to toggle power to the LCD if the baseboard uses an LCD.
- ↑ Used for onboard flash
- ↑ 12.0 12.1 Used for communication with RTC and FPGA
FPGA GPIO
The FPGA GPIO can also be accessed through the sysfs API. These are available at GPIOs 224 to 255. Not all of the reserved pins are used on this design, but they will be reserved by the kernel.
FPGA PAD | GPIO Number |
---|---|
CN1_63 | 224 |
CN1_67 | 225 |
CN1_87 | 226 |
CN1_64/MUX_AD_15 [1] | 227 |
CN2_54 [1] | 228 |
CN2_78 | 229 |
CN2_80 | 230 |
CN2_86 | 231 |
CN2_88 | 232 |
CN2_94 | 233 |
CN2_96 | 234 |
CN2_98 | 235 |
CN2_100 | 236 |
CN1_73/PUSH_SW | 255 |