TS-4900 FPGA Changelog

The FPGA is stored in /boot/ts4900-fpga.bin on most images. The latest software releases will include the latest FPGA, but older images can be updated if the md5sum matches an outdated bitstream.

Release	md5sum	Changes
ts4900-fpga-20140924.bin	d400e6c7806998e0f1b6cceb0fec022b	Initial Release
ts4900-fpga-20150326.bin	630a108d8c1af527101ee6559949b761	Register map changed significantly GPIO are the same specific registers for redirecting certain pins have been removed in favor of the crossbar Added crossbar so most FPGA pins can be mapped to almost any other FPGA pin. implemented MAX3100 SPI uart in the FPGA to add one more uart. Updated mapping for REV C boards.
ts4900-fpga-20150603.bin	75d5ef9653662dca96e2813de2804387	Includes 3 MAX3100 based UARTs Fixed ttymxc3 RXD crossbar value Work around this with older bitstreams by running "tshwctl --addr 3 --poke 0x50"
ts4900-fpga-20150930.bin	bf93c03ef914cf008287c8cd60781cc8	Corrected CTS/RTS polarity in the MAX3100 UART Corrected flipped CTS/RTS on the CPU uart for bluetooth
ts4900-fpga-20170510.bin	86c7c3d7fb9c607af1ef55e1222b4416	Fixed TXEN on CPU UARTs not correctly asserting in some multi-byte transmits