TS-4900 FPGA Functionality

The Lattice ICE40 FPGA provides auto TX enable for RS-485 half duplex, a few more DIO, the UART MUX, and it can generate clocks for use on a baseboard. Most of these registers are controlled using tshwctl in the ts4900-utils repository. The DIO can be accessed using the sysfs GPIOs 224 to 255 using the "ts4900gpio" driver. See the #GPIO section for more information on the recommended GPIO access. The below examples will communicate directly over i2c.

Usage: tshwctl [OPTIONS] ...
Technologic Systems i.mx6 FPGA Utility
     -m, --addr <address>   Sets up the address for a peek/poke
     -v, --poke <value>     Writes the value to the specified address
     -t, --peek             Reads from the specified address
     -i, --mode <8n1>       Used with -a, sets mode like '8n1', '7e2', etc
     -x, --baud <speed>     Used with -a, sets baud rate for auto485
     -a, --autotxen <uart>  Enables autotxen for supported CPU UARTs
                              Uses baud/mode if set or reads the current
                              configuration of that uart
     -c, --dump             Prints out the crossbar configuration
     -g, --get              Print crossbar for use in eval
     -s, --set              Read environment for crossbar changes
     -q, --showall          Print all possible FPGA inputs and outputs.
     -h, --help             This message

On every poweron the FPGA is programmed using the file in /boot/ts4900-fpga.bin. U-boot copies this into memory, and runs the "ice40" command to reprogram the FPGA. Without this file the FPGA will not do anything. This FPGA interfaces to the i.MX6 using the first CPU I2C bus. You can use the "tshwctl --addr <addr>" with the "--peek" or "--poke <val>" to access these registers.

Addr	Bits	Function
00	7:3	CN1_63 Crossbar
	2	CN1_63 Input Data
	1	CN1_63 Output Data
	0	CN1_63 Output Enable
01	7:3	CN1_67 Crossbar
	2	CN1_67 Input Data
	1	CN1_67 Output Data
	0	CN1_67 Output Enable
02	7:3	CN1_87 Crossbar
	2	CN1_87 Input Data
	1	CN1_87 Output Data
	0	CN1_87 Output Enable
03	7:3	ttymxc3 rxd Crossbar
	2	ttymxc3 rxd Input Data
	1	ttymxc3 rxd Output Data
	0	ttymxc3 rxd Output Enable
04	7:3	ttymxc1 CTS Crossbar
	2	ttymxc1 CTS Input Data
	1	ttymxc1 CTS Output Data
	0	ttymxc1 CTS Output Enable
05	7:3	CN2_78 Crossbar
	2	CN2_78 Input Data
	1	CN2_78 Output Data
	0	CN2_78 Output Enable
06	7:3	CN2_80 Crossbar
	2	CN2_80 Input Data
	1	CN2_80 Output Data
	0	CN2_80 Output Enable
07	7:3	CN2_86 Crossbar
	2	CN2_86 Input Data
	1	CN2_86 Output Data
	0	CN2_86 Output Enable
08	7:3	CN2_88 Crossbar
	2	CN2_88 Input Data
	1	CN2_88 Output Data
	0	CN2_88 Output Enable
09	7:3	CN2_94 Crossbar
	2	CN2_94 Input Data
	1	CN2_94 Output Data
	0	CN2_94 Output Enable
10	7:3	CN2_96 Crossbar
	2	CN2_96 Input Data
	1	CN2_96 Output Data
	0	CN2_96 Output Enable
11	7:3	CN2_98 Crossbar
	2	CN2_98 Input Data
	1	CN2_98 Output Data
	0	CN2_98 Output Enable
12	7:3	CN2_100 Crossbar
	2	CN2_100 Input Data
	1	CN2_100 Output Data
	0	CN2_100 Output Enable
13	7:2	Reserved
	1	BT_EN Output Enable
	0	Reserved
14	7:2	Reserved
	1	WL_EN Output Enable
	0	Reserved
15	7:3	Reserved
	2	BT_RTS Input value
	1:0	Reserved
16	7:3	BT_CTS Crossbar
	2	BT_CTS Input value
	1	BT_CTS Output value
	0	BT_CTS Output Enable
17	7:3	BT_RXD Crossbar
	2:0	Reserved
18	7:3	ttymxc1 RXD Crossbar
	2:0	Reserved
29	7:2	Reserved
	1	Push sw reboot enable
	0	Reserved
30	7:2	Reserved
	1	Reset (on 1)
	0	Reserved
31	7:3	Reserved
	2	Push SW Input value
	1:0	Reserved
32	7:0	RS485_CNT0 bits 23:16
33	7:0	RS485_CNT0 bits 15:8
34	7:0	RS485_CNT0 bits 7:0
35	7:0	RS485_CNT1 bits 23:16
36	7:0	RS485_CNT1 bits 15:8
37	7:0	RS485_CNT1 bits 7:0
38	7:0	RS485_CNT2 bits 23:16
39	7:0	RS485_CNT2 bits 15:8
40	7:0	RS485_CNT2 bits 7:0
41	7:0	RS485_CNT3 bits 23:16
42	7:0	RS485_CNT3 bits 15:8
43	7:0	RS485_CNT3 bits 7:0
44	7:3	SPIUART0 RX Crossbar
	2:0	Reserved
45	7:3	SPIUART1 RX Crossbar
	2:0	Reserved
46	7:3	SPIUART2 RX Crossbar
	2:0	Reserved
51	7:4	FPGA Revision
	3	B1 Strapping input value
	2	G1 Strapping input value
	1	L14 Strapping input value
	0	N14 Strapping input value
53	7:3	SPIUART0 CTS Crossbar
	2:0	Reserved
54	7:3	SPIUART1 CTS Crossbar
	2:0	Reserved
55	7:3	SPIUART2 CTS Crossbar
	2:0	Reserved

The FPGA crossbar allows almost any of the FPGA pins to be rerouted on the carrier board. All of the above registers that have a crossbar mux value can be written with these values to change the output value. When using the crossbar pins that are outputs, bit 1 should also be set to allow output enables.

Crossbar Value	Selected Function
0	Do not change
1	BT_RTS
2	BT_TXD
3	CN1_63
4	CN1_67
5	CN2_100
6	ttymxc1 RTS#
7	CN2_78
8	CN2_80
9	CN2_86
10	CN2_88
11	CN2_94
12	CN2_96
13	CN2_98
14	ttymxc3 TXD
15	ttymxc1 TXD
16	SPIUART0_TX
17	SPIUART0_TXEN
18	SPIUART0_RTS
19	SPIUART1_TX
20	SPIUART1_TXEN
21	SPIUART1_RTS
22	SPIUART2_TX
23	SPIUART2_TXEN
24	SPIUART2_RTS
25	ttymxc1 TXEN
26	ttymxc3 TXEN
27	12MHz clock
28	14MHz clock
29	24MHz clock
30	28.88MHz clock
31	GPIO

On startup these are the default values:

Pad	Default Mapping	FGPA Addr	Crossbar Reset Value
CN1_63	SPIUART1_TXEN	0	0xa1
CN1_67	SPIUART0_TXEN	1	0x89
CN1_87	GPIO 226	2	0xf8
ttymxc3 RXD	CN2_88	3	0x80
ttymxc1 CTS	BT_RTS	4	0x8
CN2_78	SPIUART0_TXD	5	0x81
CN2_80	GPIO	6	0xf8
CN2_86	ttymxc3 txd	7	0x71
CN2_88	GPIO	8	0xf8
CN2_94	SPIUART1_TXD	9	0x99
CN2_96	GPIO	10	0xf8
CN2_98	SPIUART2_TXD	11	0xb1
CN2_100	GPIO	12	0xf8
BT_CTS	ttymxc1 RTS	16	0x31
BT_RXD	ttymxc1 TXD	17	0x78
ttymxc1 RXD	BT_TXD	18	0x10
SPIUART0 RX	CN2_80	44	0x40
SPIUART1 RX	CN2_96	45	0x60
SPIUART2 RX	CN2_100	46	0x28
SPIUART0 CTS	GPIO	53	0xf8
SPIUART1 CTS	GPIO	54	0xf8
SPIUART2 CTS	GPIO	55	0xf8