TS-7100 FPGA
FPGA Registers
The TS-7100 FPGA is connected to the CPU over the WEIM bus. This provides 8-bit, 16-bit, or 32-bit access to the FPGA mapped at 0x5000_0000.
For example, to read the FPGA information at the first register of the syscon:
root@ts-imx6ul:~# memtool md -l 0x50004000+4
50004000: 00000006
| Offset | Description |
|---|---|
| 0x0000 | UART 16550 #0 |
| 0x0100 | Opencore SPI controller #0 |
| 0x0120 | Opencore SPI controller #1 |
| 0x4000 | FPGA Syscon |
FPGA 16550
This FPGA includes a 16550 UART peripheral that can be used as a standard Linux serial port. It is not recommended to interact directly with these registers.
FPGA SPI
This FPGA includes a pair of SPI master devices. These are used for the FRAM memory, accessing the flash used for the LCD splash screen image, and the LCD touch screen itself. All of these operations are handled via the Linux kernel. It is not recommended to interact directly with these registers
FPGA Syscon
The FPGA syscon is the main system control block of the FPGA. Contained in this region is the FPGA GPIO, PWM, and IRQ control. It is not recommended to interact directly with these registers unless directed to do so by other manual sections.
Some registers are dual purpose, having separate read and write functionality; while others may only have write functionality. Registers that do not read and write the same are indicated with "(RD)" and "(WR)" notation. All other registers read and write the same data set. Any unlisted register addresses are Reserved / Undefined.
- ↑ Note that this is also used for UART clock generation.
FPGA IRQs
| Bit | Description |
|---|---|
| 31:17 | Reserved |
| 16 | Touch Screen IRQ |
| 15:13 | Reserved |
| 12 | DIO Fault Breaker IRQ |
| 11 | Reserved |
| 10 | Opencore SPI Controller #1 IRQ |
| 9 | Opencore SPI Controller #0 IRQ |
| 8:1 | Reserved |
| 0 | UART #0 IRQ |