The TS-7120 FPGA is connected to the CPU over the WEIM bus. This provides 8-bit, 16-bit, or 32-bit access to the FPGA mapped at 0x5000_0000.
For example, to read the syscon 0x0:
Offset
|
Description
|
0x00
|
16550 #0
|
0x10
|
16550 #1
|
0x20
|
16550 #2
|
0x30
|
16550 #3
|
0x40
|
16550 #4
|
0x50
|
16550 #5
|
0x60
|
16550 #6
|
0x70
|
16550 #7
|
0x80
|
16550 #8
|
0x100
|
Opencore SPI controller #0
|
0x120
|
Opencore SPI controller #1
|
0x140
|
Opencore SPI controller #2
|
0x280
|
TS SDcore
|
0x4000
|
Syscon
|
Syscon
Offset
|
Bits
|
Description
|
0x0
|
31:0
|
Model ID
|
0x4
|
31:0
|
FPGA_REV_CRC32
|
0x08 (read)
|
31:20
|
Reserved
|
19
|
Toggles when data_valid ASMI output is 1
|
18
|
Illegal Erase
|
17
|
Illegal Write
|
16
|
ASMI Busy
|
15:8
|
ASMI Status out
|
7:0
|
ASMI Data out
|
0x08 (write)
|
31
|
Reserved
|
30:29
|
Operation
0
|
Read
|
1
|
Write
|
2
|
Sector Erase
|
3
|
Read Status
|
|
28:8
|
ASMI Address
|
7:0
|
ASMI data in
|
0x0c
|
31:0
|
Scratch register
|
0x10
|
15:0
|
DIO bank 0 Data Set [1]
|
0x12
|
15:0
|
DIO bank 0 Output Enable Set [2]
|
0x14
|
15:0
|
DIO bank 0 Data Clear [2]
|
0x16
|
15:0
|
DIO bank 0 Output Enable clear [2]
|
0x18
|
31:0
|
Reserved
|
0x1c
|
31:16
|
Current loop PWM #1
|
15:0
|
Current loop PWM #0
|
0x24
|
31:0
|
IRQ Status
|
0x28
|
31:16
|
ADC 1
|
15:0
|
ADC 0
|
0x2c
|
31:16
|
ADC 3
|
15:0
|
ADC 2
|
0x30
|
31:16
|
ADC 5
|
15:0
|
ADC 4
|
0x34
|
31:16
|
ADC 7
|
15:0
|
ADC 6
|
0x3c
|
31:19
|
Reserved
|
18
|
mikro_pwm_en [3]
|
17
|
hart_mode [4]
|
16
|
an_67_sel [5]
|
15:0
|
mikro_pwm
|
0x40
|
15:0
|
DIO Bank 1 Data Set [1]
|
0x42
|
15:0
|
DIO bank 1 Output Enable Set [2]
|
0x44
|
15:0
|
DIO bank 1 Data Clear [2]
|
0x46
|
15:0
|
DIO bank 1 Output Enable clear [2]
|
0x48
|
31:0
|
IRQ mask
|
- ↑ 1.0 1.1 On a write, this sets the output value. On a read this reads the current state of the pin.
- ↑ 2.0 2.1 2.2 2.3 2.4 2.5 This register is write only, and reading it back may not reflect the status value that is written.
- ↑ If PWM is not enabled this pin as available as a GPIO. When this is enabled only the PWM value is used and the corresponding GPIO bit is ignored
- ↑ 0 = all 4 HART channels RX. 1 = RX on channels 0,1 and TX on channels 2,3
- ↑ 0=STC_AN_6 is used as ADC 7. 1=STC_AN_7 is used as ADC7.
FPGA DIO Banks
Bank
|
IO
|
Description
|
0
|
15
|
sys_reset_padn
|
14
|
en_blue_led_pad
|
13
|
silab_dat_pad
|
12
|
silab_clk_pad
|
11
|
dio_14_pad
|
10
|
dio_13_pad
|
9
|
dio_12_pad
|
8
|
dio_11_pad
|
7
|
dio_10_pad
|
6
|
dio_9_pad
|
5
|
dio_8_pad
|
4
|
dio_7_pad
|
3
|
dio_6_pad
|
2
|
dio_5_pad
|
1
|
dio_4_pad
|
0
|
dio_2_pad
|
1
|
15
|
wifi_reset_padn
|
14
|
en_ls_out_1_pad
|
13
|
en_emmc_3v3_padn
|
12
|
en_gps_3v3_padn
|
11
|
en_nimbel_4v_pad
|
10
|
en_wifi_pwr_pad
|
9
|
en_ls_out_0_pad
|
8
|
en_xbee_usb_pad
|
7
|
en_hs_sw_pad
|
6
|
en_dig_in_2_3_pad
|
5
|
en_can_xcvr_padn
|
4
|
en_nimbel_3v3_pad
|
3
|
en_poe_padn
|
2
|
en_an_5v_pad
|
1
|
en_dig_in_0_1_pad
|
0
|
mikro_reset_padn
|
FPGA IRQs
Bit
|
Description
|
31:17
|
Reserved
|
16
|
cpu_touch_irq IRQ
|
15
|
wifi_irq
|
14
|
gyro_int
|
13
|
mikro_int
|
12
|
TS SDcore
|
11
|
Opencore SPI controller #2
|
10
|
Opencore SPI Controller #1
|
9
|
Opencore SPI Controller #0
|
8
|
UART #8 IRQ
|
7
|
UART #7 IRQ
|
6
|
UART #6 IRQ
|
5
|
UART #5 IRQ
|
4
|
UART #4 IRQ
|
3
|
UART #3 IRQ
|
2
|
UART #2 IRQ
|
1
|
UART #1 IRQ
|
0
|
UART #0 IRQ
|