TS-7250-V3 LCD Header

From embeddedTS Manuals

The LCD header is a 0.1" pitch 2x7 header including GPIO. This is designed around compatibility with the HD44780 LCD controller which includes our LCD-LED. The LCD Data pins (7-14) are 5V tolerant. These will output up to 3.3V, and the remaining control IO and PWM are 3.3V tolerant. The TS-7250-V3 Debian images include a command lcdmesg. This can be used to write to our LCD-LED display.

For example, this would write to the display: 

lcdmesg "line 1" "line 2"
# Messages can also be piped to lcdmesg:
echo -e "line 1\nline 2\n" | lcdmesg

For example, running: 

lcdmesg Technologic Systems

will display:

Pin 4, the LCD_BIAS pin, is used to set the contrast on the LCD. 

tshwctl --address 0x1c --poke16 0x0 # Writes minimum
tshwctl --address 0x1c --poke16 0xf # Writes maximum
Signals Pin Layout
Pin IO Type Signal
1 5V
2 GND
3 CPU 3.3V LCD_RS GPIO Chip 20a4000.gpio IO 21
4 CPU 3.3V LCD_BIAS [1]
5 CPU 3.3V LCD_EN GPIO Chip 20a4000.gpio IO 20
6 CPU 3.3V LCD_WR GPIO Chip 20a4000.gpio IO 19
7 CPU 3.3V+QS3861 LCD D1 GPIO Chip 20a4000.gpio IO 9
8 CPU 3.3V+QS3861 LCD D0 GPIO Chip 20a4000.gpio IO 10
9 CPU 3.3V+QS3861 LCD D3 GPIO Chip 20a4000.gpio IO 11
10 CPU 3.3V+QS3861 LCD D2 GPIO Chip 20a4000.gpio IO 12
11 CPU 3.3V+QS3861 LCD D5 GPIO Chip 20a4000.gpio IO 15
12 CPU 3.3V+QS3861 LCD D4 GPIO Chip 20a4000.gpio IO 16
13 CPU 3.3V+QS3861 LCD_D7 GPIO Chip 20a4000.gpio IO 17
14 CPU 3.3V+QS3861 LCD_D6 GPIO Chip 20a4000.gpio IO 18

  1. ↑ PWM duty cycle controlled by FPGA Syscon reg 0x1c. This may need to be tuned depending on the environment or altitude where the display is used.
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